有機薄膜電晶體之高介電常數介電層研究

Abstract

本篇研究利用原子層沈積(ALD)技術來成長極薄的高介電常數閘極介電層，以應用於聚3-己基噻吩(P3HT)有機薄膜電晶體，其目標是使元件的操作電壓減至最低，同時避免對場效遷移率(field-effect mobility)及元件開關比(on/off ratio)有不好的影響。我們最佳化了前驅物的暴露條件，以幫助ALD薄膜的成核及覆蓋率。氧化鋁、氧化鉿、氧化鋁-氧化鉿多層結構三種閘極介電層，在厚度小於50奈米的狀況下，皆具有不錯的性質，此厚度也低於目前文獻所報導的最小值。 由於具有高電容值及低漏電流的特性，本篇研究中的三種介電層皆成功地將元件的臨限電壓(Vth)降至3 V以下，與傳統用熱氧化矽當做閘極介電層的控制元件相比(26.7 V)，有大幅度的下降。利用厚度10奈米的氧化鋁介電層甚至可以將臨限電壓降低至1.2 V。 雖然ALD高介電介電層有效的降低了Vth，但是由於其高極性所造成的電荷捕獲效應(charge trapping effect)，降低了有機薄膜電晶體的場效遷移率。藉由在高介電介電層之表面以十八基三氯矽烷(octadecyltrichlorosilane, OTS)的自組裝層(self-assembled monolayer)做表面處理，具有低極性末端基的OTS可以避免電荷捕獲效應的發生。此自組裝層還可以進一步降低閘極漏電流，使得有機薄膜電晶體之臨限電壓皆下降至2 V以下。

This study uses atomic layer deposition (ALD) to develop ultra-thin high-dielectric-constant (high-k) gate dielectrics for poly-3-hexthylthiophene (P3HT) organic thin film transistors (OTFTs), aiming to minimize the operation voltage of the OTFTs without compromising the field-effect mobility and the on/off ratio. By optimizing the precursor exposure condition to improve the nucleation and coverage of ALD films, we demonstrate that Al2O3 films, HfO2 films and Al2O3/HfO2 alternating laminates can all achieve adequate film quality to function as the gate dielectric at thickness < 50 nm, which is significantly below the minimum thickness of high-k dielectrics previously reported for OTFTs. With high capacitance and low leakage current, all of the three types of ALD high-k dielectrics reduce the threshold voltage (Vth) of OTFT to < 3 V, down from 26.7 V of the control which uses SiO2 as the gate dielectric; the lowest Vth of 1.2 V is achieved with a 10-nm ALD Al2O3 dielectric layer. Although the ALD high-k dielectrics effectively lower the Vth, they also decrease the field-effect mobility of the resultant OTFTs due to the charge trapping effect of their high-polarity end groups. This trade-off is eliminated by modifying the surface of the high-k dielectrics with a self-assembled monolayer (SAM) of octadecyltrichlorosilane (OTS), whose low-polarity end groups prevent charge-trapping interactions with the P3HT layer. The SAM layer also reduces current leakage through the gate, thereby further lowering the Vth of all OTFTs with ALD high-k dielectrics to < 2 V.