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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41970完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Shiue-Tsung Shen | en |
| dc.contributor.author | 沈學聰 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:39:50Z | - |
| dc.date.available | 2010-10-17 | |
| dc.date.copyright | 2008-10-17 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-10-09 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41970 | - |
| dc.description.abstract | 此論文提出包括極低電壓與靜態電流的可靠性篩選策略來針對工研院所製作之8μm 製程非晶矽薄膜電晶體數位電路，並且利用burn-in 來驗證極低電壓與靜態電流所篩選的結果。由於非晶矽薄膜電晶體的可靠度不如傳統矽晶片電晶體，以burn-in 來作為傳統的可靠度測試方法可能會因提高電晶體的門檻電壓而降低良好晶片的效能，甚至破壞晶片。極低電壓與靜態電流測試因為無破壞性且成本較低而成為取代burn-in 的常用方式。在實驗中此論文使用pseudo-NMOS 的NOR-NOR 以及用pseudo-NMOS 的邏輯陣列所設計之乘3 器作為測試用電路，而正常操作電壓與極低電壓分別為10V 與7V。實驗結果顯示出極低電壓可從58 片非晶矽薄膜電晶體電路中篩選出2個通過正常電壓測試的不可靠電路，相對地靜態電流則無法有效篩選出通過正常電壓測試的不可靠電路。 | zh_TW |
| dc.description.abstract | This thesis presents a strategy, including very-low-voltage (VLV) and quiescentpower supply current (IDDQ) testing, for reliability screening of amorphous silicon thin-film transistor (a-Si TFT) digital NMOS circuits manufactured with 8μm a-Si process by Industrial Technology Research Institute. In addition, 200 seconds and 30V stress is applied for burn-in to verify the experimental results of VLV and IDDQ testing. Because the reliability of a-Si TFT is not as good as traditional Si-process,burn-in may reduce the performance of good circuits due to threshold voltage shift.Even burn-in destructs good circuits. VLV and IDDQ testing are well-known alternatives to burn-in because they are non-destructive and low cost. In our experiments, pseudo-NMOS NOR-NOR and multiplied-by-3 NOR-NOR programmable
logic array are the circuits under test (CUTs), and the nominal voltage and VLV are 10V and 7V, respectively. Our experimental results show that VLV can screen out 2 unreliable circuits passing nominal voltage testing from 58 a-Si TFT circuits. Relatively, IDDQ is not effective in screening out unreliable circuits passing nominal voltage testing. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:39:50Z (GMT). No. of bitstreams: 1 ntu-97-R95943117-1.pdf: 8899482 bytes, checksum: f1881eed7a4e0443fabae4c14040015a (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 摘要................. i
Abstract ............ ii Table of Contents ....iii List of Figures ......v List of Tables .......viii Chapter 1 Introduction .......... 1 1.1 Motivation .................. 1 1.2 Proposed Technique and Contribution ...... 2 1.3 Organization ..... 3 Chapter 2 Background ................ 4 2.1 Amorphous-Silicon Thin-film Transistor .... 4 2.1.1 Static Characteristics ........ 4 2.1.2 Typical designs using a-Si TFTs .......................... 8 2.2 Instability of a-Si TFTs ........... 11 2.3 Very-low-voltage and IDDQ Testing of CMOS Circuits .. 13 2.3.1 Very-low-voltage Testing ...... 13 2.3.2 IDDQ Testing... 15 2.3.3 Comparison of VLV, IDDQ and Burn-in ..... 18 Chapter 3 VLV Testing of a-Si TFT Circuits ...... 20 3.1 CUT Design and Defect Modeling ... 20 3.1.1 CUT Design ....................... 20 3.1.2 Defect Models in a-Si TFT Circuit ........ 23 3.2 Reliability Screening ........ 24 3.3 Simulation Results .............. 26 3.3.1 Effects of VTH Shift ........... 26 3.3.2 Effects of GIS ................. 30 iv 3.4 Experimental Results ............ 33 3.4.1 Experimental Setups .......... 33 3.4.2 VLV Experiments before Burn-in ................ 35 3.3.3 Modeling Burn-in Effects .......... 38 3.3.4 After Burn-in ............. 40 Chapter 4 IDDQ Testing of a-Si TFT Circuits ........ 49 4.1 Simulation Results ............... 49 4.1.1 Effects of VTH Shift ........ 49 4.1.2 Effects of GIS .......... 51 4.1.3 Comparison with VLV ...... 53 4.2 Experimental Results ......... 54 4.2.1 IDDQ before Burn-in ....... 55 4.2.2 IDDQ after Burn-in ......... 57 4.3 Comparison with VLV Testing ....... 59 Chapter 5 Discussions and Future Work ..... 62 5.1 Effectiveness of IDDQ and VLV testing ............ 62 5.2 Comparison of Simulation and Experimental Results ................. 62 5.3 Optimum VDD for VLV ................ 63 5.4 Effects of Burn-in .............. 64 5.5 Future Work ............ 64 Chapter 6 Summary ........... 65 Reference ............... 67 | |
| dc.language.iso | en | |
| dc.title | N型非晶矽薄膜電晶體數位電路之極低電壓與靜態電流測試 | zh_TW |
| dc.title | Very-Low-Voltage and IDDQ Testing of Amorphous Silicon TFT Digital NMOS Circuits | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),陳奕君(I-Chun Cheng) | |
| dc.subject.keyword | 非晶矽,薄膜電晶體,極低電壓測試,靜態電流測試,可靠度測試, | zh_TW |
| dc.subject.keyword | amorphous silicon,thin-film transistor,very-low-voltage testing,IDDQ testing,reliability testing, | en |
| dc.relation.page | 73 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-10-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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