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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 李建模(Chien-Mo Li) | |
dc.contributor.author | Chih-He Lin | en |
dc.contributor.author | 林志和 | zh_TW |
dc.date.accessioned | 2021-06-15T00:37:50Z | - |
dc.date.available | 2011-11-25 | |
dc.date.copyright | 2008-11-25 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-11-14 | |
dc.identifier.citation | [Al-Rawi 00] Chazi Al-Rawi, “A New Dynamic Latch Offset Measurement Technique For Offset Cancellation,” Circuit System Signal Processing, VOL.21, NO.2, pp.137-148, 2002.
[AUO 08] AU Optronics Corp. (2008). TFT-LCD_Introduction http://auo.com/auoDEV/gfx/tft-intro_lcd-theory.gif [Banihashemi 01] Mehdi Banihashemi et al., “A Low-Power, High-Resolution, 6Mhz Comparator,” European Conference on Circuit Theory and Design, VOL.3, pp.329-332, AUGUST 2001. [Banihashemi 04] Mehdi Banihashemi, “A High-Speed High-Resolution Comparator,” IEEE International Midwest Symposium on Circuit and Systems, VOL.1, pp.81-84, 2004. [ChipMOS 08] ChipMOS TECHNOLOGIES (Bermuda) LTD. (2008). Testing Services -Final Testing Equipment http://www.chipmos.com/_en/02_product/02_detail.aspx?MainID=1&SubID=12 [Chen 08] Chia-Shao Chen, “A DFT Technique for Output Offset Voltage Testing of TFT-LCD Source Driver IC,” Master Thesis, National Taiwan Univ., Taipei, Taiwan, R.O.C., 2008. [Conner 94] B. Conner, S. Velamuri, and D. Mank, “Low-power 6-bit column driver for AMLCDs,” in Dig. SID, pp.351–354, 1994. [Lin 04] San L. Lin and Samiha Mourad, “On-Chip Rise Time Measurement,” IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL.53, NO.6, pp.1510-1516, DECEMBER 2004. [Lu 08] Chih-Wen Lu and Lung-Chien Huang “A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters,” IEEE Journal of Solid-State Circuit, VOL.43, NO.2, pp.371-378, FEBRUARY 2008. [Milanesi 04] A. Milanesi and P. Buchschacher, “A novel offset cancellation circuit for TFT-LCD driver,” in Dig. SID, pp.1568–1571, 2004. [Razavi 92] Behzad Razavi and A. Wooley, “Design Technique for High-Speed, High-Resolution Comparator,” IEEE Journal of Solid-State Circuit, VOL.27, NO.12, pp.1916-1926, DECEMBER 1992. [Razavi 01] Behzad Razavi, Design of Analog CMOS Integrated Circuit. McGraw-Hill, pp.471-478, 2001. [Samid 04] Lourans Samid et al., “A Dynamic Analysis of A Latched CMOS Comparator,” Proc. of IEEE International Symposium on Circuits and Systems, VOL.1, pp.181-184, 2004. [Son 08] Young-Suk Son and Gyu-Hyeong Cho, “Design Considerations of Channel Buffer Amplifiers for Low-Power Area-efficient Column Driver in Active-Matrix LCDs,' IEEE Transactions on Consumer Electronics, VOL.54, NO.2, pp.648-656, MAY 2008. [Sumanen 02] Lauri Sumanen et al., “CMOS Dynamic Comparators for Pipeline A/D Converters,” IEEE International Symposium on Circuits and Systems, VOL. 5, pp.157-160, 2002. [TI 00] “MPT57571B-384-Channel 256-Gradation Source Driver for Color TFT LCDs Datasheet,” Texas-Instruments, (2000). Datasheet. http://www.datasheetcatalog.org/datasheet/texasinstruments/mpt57571b.pdf [Wu 88] JIEH-TSORNG WU and Bruce A. WOOLEY, “A 100-Mhz Pipelined CMOS Comparator,” IEEE Journal of Solid-State Circuit, VOL.23, NO.6, pp.1379-1385, DECEMBER 1988. [Wulff 05] Carsten Wulff and Trond Ytterdal, “0.8V 1GHz dynamic comparator in digital 90nm CMOS technology,” IEEE NORCHIP Conference 23rd, pp.237-240, 2005. [Xia 03] Tian Xia and Jien-Ching Lo, “On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization,” IEEE Proc. of the 12th Asian Test Symposium, pp.326-331, 2003. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41927 | - |
dc.description.abstract | 本篇論文提出了一個薄膜電晶體液晶顯示器源極驅動器晶片的可測試性設計,此可測試性設計可以量測輸出頻道的上升下降時間以及電壓偏差。所提出的可測試性設計在晶片上輸出頻道同時做電壓的比較,如此一來可大量減少測試機台所需要的輸入輸出針腳。根據模擬的結果可知,電壓偏差測試的準確度為2mV,上升下降時間測試的準確度為100ns。所提出的技術節省了數百個輸入輸出針腳,以及降低了百分之四十的測試時間。雖然增加了百分之十的面積成本,但可測試性設計建構在切割線上,並不會對原先的設計有所影響。源極驅動器晶片以及可測試性設計均以0.18μm的製程技術設計並且完成。 | zh_TW |
dc.description.abstract | This thesis presents a DFT technique to measure the rise/fall time and the offset of TFT-LCD source driver IC. The proposed DFT performs on-chip voltage comparison in parallel so the required number of tester channels <pins> is greatly reduced. According to simulation results, the accuracy of offset testing is 2mV and the rise/fall tine testing is 100ns. The proposed technique saves hundreds of I/O pins and reduces the total test time by 40%. Although the area penalty is 10%, the DFT circuitry is implemented on the scribe line so it is non-intrusive to the original design. The DFT has been implemented on an industrial design in 0.18μm technology. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:37:50Z (GMT). No. of bitstreams: 1 ntu-97-R95943096-1.pdf: 18510399 bytes, checksum: b89b9a98883c1264095db0f0e6829d88 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | 摘要 i
Abstract ii 目錄 iii 圖目錄 v 表目錄 ix 第一章 序論 1 1.1 論文背景與動機 1 1.2 技術與論文貢獻 3 1.3 論文組織 6 第二章 論文相關背景與研究 7 2.1 薄膜電晶體液晶顯示器源極驅動器(TFT-LCD Source Driver)基本介紹 7 2.1.1 源極驅動器基本原理及運作 7 2.1.2 源極驅動器規格 12 2.2 上升以及下降時間量測相關研究 13 2.3 比較器電路相關研究 19 2.3.1常見的偏差消除機制 19 Input Offset Storage(IOS) 19 Output Offset Storage(OOS) 20 2.3.2 其他比較器的偏差消除方法 22 2.3.3 其他比較器電路 23 第三章 源極驅動器可測試性設計架構 26 3.1 DfT的整體架構 26 3.2 DfT整體架構分析 31 3.2.1 類比多工器(Analog Multiplexer) 31 3.2.2 DfT Cell電路分析 34 輸入取樣電路(Input Sampling Network) 34 比較器(Comparator) 37 掃描正反器(Scan Flip-Flop ) 46 3.3 上升時間和下降時間的測試方法以及模擬結果 47 3.4 準確度估計以及模擬 53 3.4.1 比較器準確度模擬及分析 53 3.4.2 上升時間以及下降時間準確度估算以及模擬結果 55 第四章 實作結果以及ATE測試流程 56 4.1 DfT在源極驅動器上的佈局 56 4.2 佈局後DfT模擬結果 59 4.2.1 IR效應對VDD以及VSS所造成的影響以及模擬結果 59 4.2.2 佈局後DfT模擬結果 62 4.3 DfT的設計規格 67 4.4 ATE測試流程(ATE Testing Flow) 69 4.4.1 校正程序 69 4.4.2 測試頻道偏差測試 72 4.4.3 上升以及下降時間測試 73 第五章 討論與未來工作 77 5.1 縮減DfT的面積 77 5.2 減輕IR效應的影響 78 5.3 增加上升以及下降時間的準確度 79 第六章 結論 80 參考文獻 81 | |
dc.language.iso | zh-TW | |
dc.title | 液晶顯示器源極驅動器晶片上升時間以及下降時間測試的可測試性設計 | zh_TW |
dc.title | A DfT Technique for Rise Time and Fall Time Testing of LCD Source Driver IC | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),卜令楷(Lin-Kai Bu) | |
dc.subject.keyword | 可測試性設計,源極驅動器晶片,上升時間,下降時間, | zh_TW |
dc.subject.keyword | DfT,Source driver,rise time,fall time, | en |
dc.relation.page | 83 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-11-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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