以脈衝放電方式之反或邏輯閘型態內容定址記憶體

Abstract

低功率超大型積體電路是現在最重要的課題之一；在晶片實作上，因為製程的演進使得晶片面積越來越小以及技術的增進使得操作頻率越來越高且電晶體數量越來越多，因此在單位面積上的熱與功率消耗就越來越高，直接影響晶片的效能，因此設計技術的演進越來越朝低功率前進。 內容定址記憶體主要是應用在晶片網路架構上，像是交換器、路由器及網路介面等等硬體；因此對內容定址記憶體的改良便是在網路設備的效能上有最直接的影響。一直以來，內容定址記憶體的改進從NAND-Type CAM這種省電但耗時的架構以及NOR-Type CAM這種省時但耗電的架構一直在做架構演進，使其能兼具兩者優點。 在本論文中，我們提出了一個藉由匹配與不匹配之間的寄生電容差異所導致對固定的脈衝放電產生不同電壓差異的技術來設計出一個低擺幅(low swing)的反或邏輯閘型態的內容定址記憶體。根據實驗結果，可以將功率消耗節省約88%以及所需延遲減少78%。

The design of the low power VLSI is one of the most important issue; in chip design, because the development of the process causes smaller and smaller chip area and the development of the technology makes higher and higher frequency and the huge increase of the number of transistors. Therefore, the unit area of the chip produces high power consumption and heat, and the heat directly affects the performance. Therefore, the development of the design technology goes on low power technology. Content Addressable Memories (CAM) is mainly applied in network architecture hardware on chip such as switch, router and network interface; therefore, the improvement of CAMs directly affects the performance of the network application. In the history of CAMs, the improvement of CAMs begins from the NAND-Type CAM which has the characteristic of saving power but spending much time and the NOR-Type CAM which has the characteristic of saving time but spending much power, and the new architecture is traded off from these two architectures to save power and time. In this master thesis, we design a low swing NOR-Type CAM by the pulse discharge technology. The approach is to produce different voltage drop by different capacitances through charge sharing characteristic in the condition of providing the same discharge at calculation state. According to the simulation result, we save 88% power consumption and 78% delay.