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標題: | 矽鍺量子井/量子點元件和馬鞍形電晶體 SiGe Quantum-Well/Quantum-Dot Devices and Saddle FinFETs |
作者: | Ping-Sheng Kuo 郭平昇 |
指導教授: | 劉致為 |
關鍵字: | 矽鍺,金氧半,相斥位障,蕭基,馬鞍形場效電晶體, SiGe,MIS,repulsive barrier,Schottky,saddle FinFETs, |
出版年 : | 2009 |
學位: | 博士 |
摘要: | 本論文中,我們研究矽鍺金氧半元件並且分為實驗部分和模擬部分。
首先,因為矽鍺量子點可以束困電洞,我們首次發現矽鍺量子點的金氧半穿隧二極體會有電洞電流阻礙的現象發生。五層自我生成的矽鍺量子點,每層以一層74奈米的矽為間隔,並在最上方蓋一層130奈米的矽。在結構中加入矽鍺量子點可以在價電帶束困電洞並且形成位障來阻擋電洞電流,實驗發現不管是正偏壓或負偏壓電流都被有效降低。 金屬-氧化物-N型鍺結構被製作成光偵測器。我們使用鋁和鉑當電極去研究此光偵測器的傳輸機制。在負偏壓時,鋁電極元件的暗電流是由在空乏區內由於熱產生的少數載子和從鋁穿隧到N型鍺導電帶的電子電流所組成。然而對鉑電極元件而言,由於鉑(5.65電子伏特)相對鋁(4.15電子伏特)具有較高的金屬功函數,所以從金屬穿隧到N型鍺導電帶的電子電流將被大大的降低。 我們製作N型矽/矽鍺/矽量子井的蕭基二極體並利用鉑當電極,我們發現由於矽鍺量子井在價電帶的能帶偏差所引起的電洞累積會縮短空乏區的寬度。在逆偏壓時,空乏區的縮短會增加電容和電流。傳統的電容電壓量測方式不能用來量測矽/矽鍺/矽量子井結構的消基二極體的位障。 第二部分是模擬,分為應用在動態記憶體上的馬鞍形場效電晶體和矽/鍺/矽量子井結構P型場效電晶體。由於矽/鍺/矽量子井結構會導致空乏區的縮短,因此不需要額外的摻雜去防止源極和汲極的貫穿。對50奈米以下的動態記憶體而言,馬鞍形場效電晶體比鰭片場效電晶體擁有較低的漏電和較佳的特性,我們提出新結構和改變摻雜方式去降低漏電和閘極電容。 In this dissertation, the SiGe metal-insulator-semiconductor devices are studied and we divide into the experiment part and the simulation part. First, the blockage of hole transport due to excess holes in SiGe dots was observed in the metal-oxide-semiconductor tunneling diodes for the first time. The 5 layers of self-assembled SiGe dots are separated by 74 nm Si spacers and capped with a 130nm Si. The incorporation of SiGe dots confines the excess holes in the valence band, and forms a repulsive barrier to reduce the hole transport current at positive and negative gate biases. A metal/oxide/n-Ge structure has been utilized as a photodetector. We use Al and Pt as the gate electrodes to evaluate the transport mechanism of the MOS detector. At negative gate bias, the dark current of the Al gate detector is composed of the thermal generation of minority carriers in the depletion region and the electron current tunneling from Al to conduction band of the n-type Ge substrate. However, for the Pt gate detector at negative gate bias, the electron tunneling from Pt to conduction band of the n-type Ge is greatly reduced due to the large work function of Pt (5.65 eV) as compared to Al (3.15 eV). The hole confinement due to the valence band offset of the Si/SiGe/Si quantum well causes the shrinkage of depletion region for the n-type Si/SiGe/Si Schottky barrier diodes with Pt gates. The shrinkage of depletion region at reverse bias increases capacitance and current. The conventional capacitor-voltage method can not be used to measure the barrier height of Si/SiGe/Si quantum well Schottky diodes due to the shrinkage of depletion region. The second part is the simulation work of saddle FinFETs for DRAM applications and Si/Ge/Si QW pFETs. No punch-through anti-doping is required for the Si/Ge/Si pFETs due to the shrinkage of depletion region. The saddle FinFETs are demonstrated to be more suitable than the bulk FinFETs for sub-50nm DRAM applications. We proposed new structure and optimized the doping profiles in source/drain to reduce the leakage current and word-line capacitance. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41449 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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