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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 曹恆偉(Hen-Wai Tsao) | |
dc.contributor.author | Po-Hsun Chen | en |
dc.contributor.author | 陳博勳 | zh_TW |
dc.date.accessioned | 2021-06-15T00:14:28Z | - |
dc.date.available | 2010-06-30 | |
dc.date.copyright | 2009-06-30 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-06-26 | |
dc.identifier.citation | [1] H.-H Chang, J.-W Lin, C.-Y Yang and S.-I Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle”, IEEE J. Solid-State Circuits, Vol. 37, pp.1021-1027, Aug. 2002.
[2] H. Notani et al., “A 622-MHz CMOS phase-locked loop with rechargetype phase frequency detector,” in Symp. VLSI Circuits Dig. Tech. Papers, June 1994, pp. 129–130 [3] J.-G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques”, IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996. [4] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, and H.-K. Lim, “A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL”, IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997. [5] Hsiang-Hui Chang; Jung-Yu Chang;Chun-Yi Kuo and Shen-Iuan Liu 'A 0.7-2-GHz self-calibrated multiphase delay-locked loop' IEEE J. Solid-State Circuits, Vol 41, May 2006 [6] I. A. Young, J. K. Greason and L. L. Wong, “A PLL clock generator with 5 to 110MHz of lock range for moicroprocessors”, IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992. [7] Chorng-Sii Hwang; Chin-Wei Sung and Hen-Wai Tsao; 'Continuous time digitizer utilizing multiphase sampling technique' in Proc. IEEE Conf. Rec. NSS, vol.1, pp.374 – 378, Oct. 26 2007-Nov. 3 2007 [8] P. Larsson, “A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability”, IEEE J. Solid-State Circuits, vol. 34, pp. 1951-1960, Dec. 1999. [9] F.-M. Gradner, “Charge-pump phase-locked loops”, IEEE Trans. Communications, vol.28, pp.1849-1858, Nov. 1980. [10] Rhee, W.,〝Design of high-performance CMOS charge pumps in phase-locked loops〞, Inter. Symposium Circuits and System, vol 2, 30 May-2 June 1999 [11] D.-K. Jeong, G. Borriello, D.A. Hodges and R. H. Katz, “Design of PLL-based clock gerneration circuits”, IEEE J. Solid-State Circuits, vol.22,pp.255-261, Apr. 1987. [12] B. Razavi, Design of Analog CMOS integrated Circuit Design, New York : McGraw-Hill, 2001 [13] F.-R., R.; Dally, W.; H.-T. Ng; Senthinathan, R.; Lee, M.-J.E.; Rathi, R.; Poulton and J. 'A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips' IEEE J. Solid-State Circuits,Vol. 37, pp.1804 – 1812, Dec. 2002 [14] T.-C. Lee and K.-J. Hsiao 'The design and analysis of a DLL-based frequency synthesizer for UWB application' IEEE J. Solid-State Circuits, Vol. 41, pp.1245 – 1252, June 2006 [15] Chien, G. and Gray, P.R. 'A 900-MHz local oscillator using a DLL-based frequencymultiplier technique for PCS applications', in ISSCC 2000 Dig. Tech. Papers, Feb. 2000, pp.202 – 203. [16] C. Kim, I.-C. Hwang and S.-M. Kang, “A low-power small-area +- 7.28-ps-jitter 1-GHz DLL-based clock generator“, IEEE J. Solid-State Circuits, vol.37, pp.1414-1420, Nov. 2002. [17] Kim, J.-H.; Kwak, Y.-H.; Kim, M.; Kim, S.-W. and Kim, C. 'A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling', IEEE J. Solid-State Circuits, Vol. 41, pp.2077 – 2082, Sept. 2006 [18] Kyunghoon Chung; Jabeom Koo; Soo-Won Kim and Chuhvoo Kim 'An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling', in Proc. IEEE Asia- Pacific Conference on Advanced System Integrated Circuits, pp.276 - 279 Nov. 2007 [19] Jabeom Koo; Sunghwa Ok and Chulwoo Kim, 'A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock' IEEE Tran. Circuits and System II, vol. 56, pp.21-25 Jan. 2009 [20] H.-H. Chang, “Design and Implementation of CMOS Digital/Analog Delay-Locked Loops”, Ph.D. Dissertation, NTU, 2004. [21] 劉深淵, 楊清淵著, 鎖相迴路, 滄海書局, 2006. [22] R.-L. Aguiar and D.-M. Santos, “Oscillatorless clock multiplication “, IEEE Solid-State Circuits, vol.4, pp. 630 – 633, May 2001. [23] S.-I. Liu; J.-H. Lee and H.-W. Tsao, “Low-power clock-deskew buffer for high-speed digital circuits” , IEEE J. Solid-State Circuits, Vol. 34, pp.554 – 558, April 1999. [24] W. J. Dally and J. Poulton, Digital System Engineering. Cambridge, U.K., Cambridge Univ. Press, 1998 [25] J. E. McNamara, Technical Aspects of Data Communication, 2nd ed., Digital Press, Bedford, MA, 1982 [26] D. Santos, S. Dow, J. Flasck, and M. Levi, “A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip”, IEEE Trans. Nucl. Sci., vol. 43, pp. 1717–1719, June 1996. [27] A. Mantyniemi, T. Rakhonen, and J. Kostamovaara, “An integrated 9-channel time digitizer with 30-ps resolution”, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 266–267, Feb. 2002. [28] C.-T. Gray, W.-T. Liu, W. Noije, T. Hughes and R.-K. Cavin III, “A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution”, IEEE J. Solid-State Circuits, vol. 29, pp. 340-349, Mar. 1994. [29] P. Dudek, S. Szczepanski and J.-V. Hatfield, “A high resolution CMOS time-to-digital converter utilizing a vernier delay line”, IEEE J. Solid-State Circuits, vol. 35, pp. 240–247, Feb. 2000. [30] P. Chen and S.-I. Liu, “A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution”, in Proc. Custom Integr. Circuits Conf., pp. 605–608, May 1999 [31] J.-P. Jansson, A. Mantyniemi and J. Kostamovaara, “A CMOS time-to-digital converter with better than 10 ps single-shot precision”, IEEE J. Solid-State Circuits, vol. 41, pp. 1286-1296, Mar. 2006. [32] Jingcheng Zhuang; Qingjin Du and Kwasniewski, T. 'A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer', in Proc. IEEE Custom Integrated Circuits Conf., pp.301 – 304, Sept. 2003 [33] R.-M. Weng; T.-H. Su; C.-Y. Liu and Y.-F Kuo; 'A CMOS Delay-Locked Loop Based Frequency Multiplier for Wide-range Operation', in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.419 – 422, Dec. 2005 [34] B. Razavi, RF microelectronics, New York : Prentice-Hill, 1998 [35] Roland E. Best, Phase-Locked Loop, McGraw-Hill, 2003 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41223 | - |
dc.description.abstract | 隨著大型積體電路製程的進步,時脈產生器被廣泛應用於各類型電路系統,例如微處理器系統、記憶體積體電路、有線與無線網路信號傳輸…等等,都需要產生所需頻率的倍頻時脈,藉以做為同步時脈操作,或者混波降頻的之用途。常見的時脈產生器基礎架構設計方式可分為鎖相迴路(Phase-Locked Loop, PLL)與延遲鎖定迴路(Delay-Locked Loop, DLL)。傳統設計多採用前者;但延遲鎖定迴路具有容易設計的特性,因其本身為二階系統穩定度較佳,在迴路濾波器設計上僅需一個電容,面積可以有效縮小。並同時具有低時間抖動特性。
本論文提出在典型架構之脈波產生器內增加更多的倍頻數選擇(增加至12種);設計新型電路如致能短脈波產生器(Enabled Short-Pulse Generator, ESPG),差動切換脈波拴鎖電路(Differential Toggle-Pulsed Latch, DTPL)來合成所需之高速合成差動輸出時脈。為了增加應用層面,輸出脈波為雙端輸出且不受延遲鎖定迴路的多相位影響。本研究使用CMOS 0.18μm 1P6M製程,在輸入操作頻率為300MHz∼400MHz下,輸出頻率範圍為150MHz∼1.8GHz,整體晶片核心面積為241 μm x 316 μm。 | zh_TW |
dc.description.abstract | As the progress of the VLSI technologies, clock generator needed to mix a required clock as an operation of the synchronization or the degradation of the frequency, has been widely implemented in many applications of circuit systems, such as Microprocessor, Memory Integrated Chip, wireless communication. The ordinary structure of a clock generator could be classified into two kinds. One is phase-locked loop(PLL);the other is delay-locked loop(DLL). The former one is usually adopted by conventional designer but DLL is more suggested because of its stability and easily designed architecture. Furthermore, DLL contents better performance of jitter.
There are 12 choices of multiplication factors in the scheme we proposed. The newly circuits, such as enabled short-pulse generator(ESPG), differential toggle-pulsed latch(DTPL), are used to combine the multiphase of the DLL and generate the output clock. The output clock, which is fully differential output to increase the level of applications, wouldn’t be affected by the duty cycle of DLL’s multiphase. CMOS 0.18μm process is used in our work. The output frequency of the reference is between 150MHz to 1.8GHz from the input frequency 300MHz to 400MHz. The chip core area is 0.241mm x 0.316mm. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:14:28Z (GMT). No. of bitstreams: 1 ntu-98-R95943100-1.pdf: 4791998 bytes, checksum: 6d898271b813f9abf0995fd26555f011 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 中文摘要 I
Abstract II Contents III List of Figures VI List of Tables IX Chapter 1 緒論 1 1.1 動機 1 1.2 論文架構 2 Chapter 2 延遲鎖定迴路 3 2.1 延遲鎖定迴路介紹 3 2.2 延遲鎖定迴路的特性分析 6 2.3 延遲鎖定迴路之諧波鎖定 9 2.4 延遲鎖定迴路之組成方塊 11 2.4.1相位頻率/相位偵測器 11 2.4.2充電泵 16 2.4.3 電壓控制延遲線 20 2.5 延遲鎖定迴路其它應用 22 2.5.1 時脈誤差修正電路 23 2.5.2 資料鏈結 24 2.5.3 時間對數位轉換器 25 Chapter 3 以延遲鎖定迴路為基礎之可程式化頻率倍頻器 27 3.1 基本理論介紹 27 3.2 各類頻率倍頻器介紹 28 Chapter 4 新型差動切換脈波拴鎖電路之可程式化時脈產生器 40 4.1 新型差動切換脈波栓鎖電路之可程式化時脈產生器 40 4.2 可程式化時脈產生器內部電路 43 4.2.1電壓壓控延遲單元 43 4.2.2相位頻率偵測器和充電泵 45 4.2.3頻率倍增器 48 4.2.3數位控制單元 55 Chapter 5 模擬分析和量測結果 57 5.1 設計流程 57 5.2 環境模擬結果 59 5.3 量測環境 65 5.4 量測結果 68 5.5 結論 75 Chapter 6 總結與展望 78 6.1 總結 78 6.2 展望 78 Bibliography 80 | |
dc.language.iso | zh-TW | |
dc.title | 使用新型差動切換脈波拴鎖電路之延遲鎖定迴路型式可程式化時脈產生器設計 | zh_TW |
dc.title | Design of DLL-Based Programmable Clock Generator Using Differential Toggle-Pulse Latch | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 黃崇禧(Chrong-Sii Hwang) | |
dc.contributor.oralexamcommittee | 楊?頡(Rong-Jyi Yang),楊清淵(Ching-Yuan Yang),翁若敏(Ro-Min Weng) | |
dc.subject.keyword | 時脈產生器,延遲鎖定迴路,差動切換脈波拴鎖電路, | zh_TW |
dc.subject.keyword | Clock Generator,Delay-Locked Loop,Differential Toggle-Pulsed Ltach, | en |
dc.relation.page | 83 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-06-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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