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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 賴飛羆(Fei-pei Lai) | |
dc.contributor.author | Chien-Yu Pan | en |
dc.contributor.author | 潘建宇 | zh_TW |
dc.date.accessioned | 2021-06-14T17:22:23Z | - |
dc.date.available | 2018-12-31 | |
dc.date.copyright | 2008-08-05 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-07-24 | |
dc.identifier.citation | [1] Benini, L., L. Benini, and G. De Micheli, Networks on chips: a new SoC paradigm. Computer, 2002. 35(1): p. 70-78.
[2] Kumar, S., et al. A network on chip architecture and design methodology. in IEEE Computer Society Annual Symposium on VLSI 2002. [3] Pierre, G. and G. Alain, A generic architecture for on-chip packet-switched interconnections, in Proceedings of the conference on Design, automation and test in Europe. 2000, ACM: Paris, France. [4] Pande, P.P., et al. Design of a switch for network on chip applications. in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on. 2003. [5] Karim, F., et al., An interconnect architecture for networking systems on chips. Micro, IEEE, 2002. 22(5): p. 36-45. [6] Glass, C.J. and L.M. Ni. The Turn Model for Adaptive Routing. in Computer Architecture, 1992. Proceedings., The 19th Annual International Symposium on. 1992. [7] Ge-Ming, C., The odd-even turn model for adaptive routing. Parallel and Distributed Systems, IEEE Transactions on, 2000. 11(7): p. 729-738. [8] Jingcao, H. and R. Marculescu. Energy-aware mapping for tile-based NoC architectures under performance constraints. in Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific. 2003. [9] Nickray, M., M. Dehyadgari, and A. Afzali-kusha. Power and delay optimization for network on chip. in Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on. 2005 [10] Marcon, C., et al. Exploring NoC mapping strategies: an energy and timing aware technique. in Design, Automation and Test in Europe, 2005. Proceedings. 2005. [11] J.D. Wang, 'Low Power Mapping of Cores onto Hybrid NoC Architecture,' M.S. thesis, Department of Computer Science and Information Engineering, National Taiwan University, Taiwan, R.O.C., 2007. [12] AMBA bus specification ,http://www.arm.com/ . [13] 'AMBATM Specification Revision 2.0,' May 13, 1999 [14] Young-Sin, C., C. Eun-Ju, and C. Kyoung-Rok, Modeling and analysis of the system bus latency on the SoC platform, in Proceedings of the 2006 international workshop on System-level interconnect prediction. 2006, ACM: Munich, Germany. [15] Erik, B.v.d.T. and G.J. Egbert. Mapping of MPEG-4 decoding on a flexible architecture platform. 2001: SPIE. [16] Dick, R.P., D.L. Rhodes, and W. Wolf. TGFF: task graphs for free. in Hardware/Software Codesign, 1998. (CODES/CASHE '98) Proceedings of the Sixth International Workshop on. 1998. [17] C. A. Zeferino, M. E. Kreutz, A. A. Suisn, “RASoC: a router soft-core for networks-on-chip,” in Proc. of Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp.198-203, Feb, 2004. [18] C. A. Zeferino, A. A. Suisn, “SoCIN: a parametric and scalable network-on-chip,” in Proc. of Symposium on Integrated Circuits and System Design, vol. 3, pp.169-174, Sept, 2003. [19] C.A. Zeferino, F. G. M. E. Santo, A. A. Suisn, “ParIS: a paramaterizable interconnect switch for network-on-chip,” in Proc. of Symposium on Integrated Circuits and System Design, pp. 204-209, Sept, 2004. [20] T. Wolkotte, G. J. M. Smit, G. K. Rauwerda, L. T. Smit, “An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip,” in Proc. of IEEE International Parallel and Distributed Processing Symposium, pp.155a-155a, April, 2005. [21] Task Graph For Free. http://ziyang.ece.northwestern.edu/~dickrp/tgff/. [22] Wein-Tsung, S., et al. A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. in Networks-on-Chip, 2007. NOCS 2007. First International Symposium on. 2007. [23] Murali, S. and G. De Micheli. Bandwidth-constrained mapping of cores onto NoC architectures. in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. 2004 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41184 | - |
dc.description.abstract | 隨著新技術的開發,允許我們將數百萬個電晶體整合入單一晶片.這些複雜的系統需要特殊的溝通資源去處理緊湊的設計需求.網路晶片(Networks-on-Chip)適合去處理這樣的需求,因為它提供了高擴充性、高重複使用性和高可靠性.二維網格(two–dimension mesh)是一種很受歡迎的網路晶片拓蹼.但是它的缺點是網路上傳輸距離比較遠所造成的延遲.在二維網格的中心常常形成熱點和壅塞.藉由將二維網格切割成幾個子系統並且以網路連接這些子系統,匯流排晶片網路混合系統可以減少二維網格傳輸時經過節點數過多的問題和其中心容易發生的壅塞問題.然而,要建置一些即時的應用在匯流排晶片網路混合系統時,有效的配置方法是必須被考慮的.在這篇論文中,我們提出了一個配置演算法在頻寬限制下可以將矽智產 (Intellectual Property)配置到匯流排晶片網路混合系統中,並且可以減少傳輸延遲和經過的節點數. | zh_TW |
dc.description.abstract | New technologies allow the implementation of complex systems-on-chip (SoC) with hundreds of millions transistors integrated onto a single chip. These complex systems need special communication resources to cope with very tight design requirements. A NoC is suitable to deal with such requirements, since it provides high scalability, reusability and reliability. A popular network topology for Network-on-Chip implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. It often haves congestions or hotspots developed in the center of the mesh. By partitioning a two dimensional mesh into several sub-systems and connecting them using a network, Bus-NoC hybrid system can reduce the average number of hops for global traffic and the congestion in the center of the mesh. However, an efficient mapping strategy that can minimize the system communication delay of the system must be taken into account by the designer when regarding some real time application. In this theis, we present an algorithm that maps the cores onto a Bus-NoC hybrid system under the bandwidth constrains, and take advantage of locality to minimize the average communication delay and hop counts incurred by global traffic. | en |
dc.description.provenance | Made available in DSpace on 2021-06-14T17:22:23Z (GMT). No. of bitstreams: 1 ntu-97-R95922166-1.pdf: 1213319 bytes, checksum: 02bbf1c562b691337851de975ca834c5 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | 1.1 Concept of NoC 1
1.2 Basic architecture of NoC 1 1.3 Bus-NoC hybrid system 2 1.4 Motivation and Goal 4 1.5 Thesis organization 5 Chapter 2 Related Work and Background 6 2.1 NoC topology 6 2.1.1 CLICHÉ 6 2.1.2 Torus and Fold 7 2.1.3 SPIN 9 2.1.4 BTF 10 2.1.5 OCTAGON 11 2.2 NoC Routing Algorithm 12 2.2.1 XY-routing 13 2.2.2 West-first routing algorithm 14 2.2.3 Odd-Even turn model 14 2.3 Switching methods 15 2.4 Related work 18 Chapter 3 Platform description and Problem definition 19 3.1 Platform description19 3.1.1 AMBA 19 3.1.2 Introduction to AMBA AHB 20 3.1.3 AHB interface 22 3.1.4 Network interface 25 3.2 Latency model 25 3.2.1 Latency model of bus 25 3.2.2 Latency model of NoC 26 3.3 Problem definition 26 Chapter 4 Proposed Method 30 4.1 Application-specific design procedure for Bus-NoC hybrid system 30 4.2 System partition31 4.3 Mapping 33 4.3.1 Mapping phase 33 4.3.2 Optimization phase 35 Chapter 5 Experiment environment and results 37 5.1 Experiment environment 37 5.2 Experiment results 40 Chapter 6 Conclusion 43 REFERENCE 44 | |
dc.language.iso | en | |
dc.title | 匯流排及晶片網路混合架構下之低延遲特定應用配置方法 | zh_TW |
dc.title | A Latency Aware Application Specific Core Mapping Algorithm for Bus-NoC Hybrid System | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張延任(Yen-Jen Chang),李鴻璋(Hong-Zhang Li),林正偉(Jeng-Wei Lin),蔡坤霖(Kun-Lin Tsai) | |
dc.subject.keyword | 網路晶片,壅塞,延遲,匯流排晶片網路系統,配置演算法, | zh_TW |
dc.subject.keyword | NoC,Congestion,Latency,Bus-NoC hybrid system,mapping algorithm, | en |
dc.relation.page | 46 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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