具有相位校正電路的多相位時脈產生器

Abstract

經銅線傳輸的百億位元乙太網路系統為下一世代的乙太網路系統，傳輸速率可達每秒百億位元，傳輸的距離可達100公尺。在高速的資料傳輸下，類比及數位電路的設計都非常的嚴峻。百億位元乙太網路系統的收發器架構在以一個每秒1600萬次取樣的數位類比轉換器及一個每秒800萬次取樣的數比數位轉換器的基礎之上，而為了重設被接收資料的時序，必需設計一個多相位時脈產生器，提供準確的解析度以達成對資料精準的取樣。 本論文中，提出一個提供833百萬赫茲、132個相位並具有校準電路的時脈產生器的架構，可利用於百億位元乙太網路系統的收發器的類比前端。使用兩個延遲鎖定迴路(DLL)組合成多相位時脈產生器，所產生的相位數為兩個延遲鎖相迴路的延遲單元數的乘積，可以很有效率的產生多個相位。本論文也提出一個校正電路，利用循序的方法比較每一個輸出的相位，以校正每一個延遲單元之前的不匹配。在校正電路之中，只使用一組充電泵與相位偵測器，所以所有的訊號都會經過相位的路徑，元件之間以及路徑之間的不匹配可因此而降低。 使用0.13微米互補金氧半導體製程來製作的多相位時脈產生器，在1.2伏特的電壓之下，總共消耗67.2毫瓦的功率。在總共132個相位輸出中，DNL為4.83個LSB，INL為4.47個LSB。輸出時脈的抖動方均根值為5.8 ps，而抖動峰值為54.6ps。

10GBASE-T is the next-generation 10Gbps copper cable Ethernet network and transmitting distance is up to 100 meters of a standard CAT-6 cable. The digital and analog circuits under high speed data transmission are very critical for 10GBASE-T Ethernet system. The transceiver architecture of 10GBASE-T is based on 1600-Msample/s DACs and 800-Msample/s ADCs. In order to retime the received data, a multiphase clock generator must be designed to provide fine resolution of timing to sample the data precisely. In this thesis, an 833-MHz 132-Phase clock generator with self-calibration circuits for the analog front-end of 10GBASE-T Ethernet system is proposed. Two delay-locked loops (DLLs) are used to produce phases efficiently because the number of output phase is the product of the stage numbers of the two DLLs. A DLL calibration algorithm which uses the sequential comparison method is also proposed to calibrate the mismatch between delay cells. Only one charge pump and one phase detector are needed in calibration circuits and all output signals go through the same path. Consequently, the effect of the mismatch of the devices can be avoided and the mismatch of the path can be eliminated. This multiphase clock generator with self-calibration circuits have been fabricated in a 0.13-μm CMOS technology, while dissipating 67.2 mW from a single 1.2-V power supply. The DNL is 4.83 LSB and INL is 4.47 LSB with totally 132 phases output. The rms jitter of the output clock signal has been measured to be 5.8 ps, and the peak-to-peak jitter has been measured to be 54.6 ps.