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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40625完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張時中 | |
| dc.contributor.author | Wei-Chuan Lin | en |
| dc.contributor.author | 林韋銓 | zh_TW |
| dc.date.accessioned | 2021-06-14T16:53:43Z | - |
| dc.date.available | 2009-08-04 | |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-29 | |
| dc.identifier.citation | [1] F. M. Garraffo, “Research & development investments and performance in high technology industries: some evidence from semiconductor firms,” Proceedings of the 2000 IEEE international conference, 1, 234-239, 2004.
[2] International Technology Roadmap for Semiconductors (ITRS), 2005. [3] T. P. Ryan, Statistical Methods for Quality Improvement. New York: Wiley, 1989. [4] C. M. Fan, R. S. Guo, S. C. Chang, and J. S. Wei, “SHEWMA: an End-of-line SPC Scheme Using Wafer Acceptance Test Data,” IEEE Transactions on Semiconductor Manufacturing, vol. 13, no. 3, 344-357, 2000. [5] A. Chen, R. S. Guo, and P. J. Yeh, “An effective SPC approach to monitoring semiconductor manufacturing processes with multiple variation sources,” International Symposium on Semiconductor Manufacturing, Tokyo, Japan, 2000. [6] C. M. Fan, R. S. Guo, A Chen, K. C. Hsu, C. S. Wei, “Data Mining and Fault Diagnosis Based on Wafer Acceptance Test Data and In-Line Manufacturing Data”; IEEE International Semiconductor Manufacturing Symposium; Oct. 8-10, 171-174, 2001. [7] D. Braha and A. Shmilovici, “Data Mining for Improving a Cleaning Process in the Semiconductor Industry,” IEEE Transactions on Semiconductor Manufacturing, Vol.15, No.1, 91-101, 2002. [8] F. Mieno, T. Sato, Y. Shibuya, K. Odagiri, H. Tsuda, and R. Take, “Yield improvement using data mining system semiconductor manufacturing,” IEEE International Symposium on Conference Proceedings, pp. 391-394, 1999. [9] C. K. Tsai, “Intelligent End-of-Line Process Diagnosis for Semiconductor Fabrication,” Graduate Institute of Electrical Engineering, College of Electrical Engineering and Computer Science, National Taiwan University, 2007. [10] S. C. Hsu and C. F. Chien, “Hybrid Data Mining Approach for Pattern Extraction from Wafer Bin Map to Improve Yield in Semiconductor Manufacturing,” International Journal of Production Economics, 2007. [11] S. F. Liu, F. L. Chen and W. B. Lu, 'Wafer Bin Map Recognition Using a Neural Network Approach,' International Journal of Production Research, Vol.40, No.10, 2207-2224, 2002. [12] Motorola’s Engineering Data Analysis System: 10 Years Of Analytical Excellence: http://www2.sas.com/proceedings/sugi25/25/ad/25p044.pdf [13] SAS, The SAS Enterprise Intelligence Platform : http://www.sas.com/technologies/architecture/ [14] Yield Dynamics, Yield Management:http://www.ydyn.com/products/genesis_enterprise.htm [15] Synopsys, PrimeYield Tool Suite:http://www.synopsys.com/products/primeyield/primeyield.html [16] D. Fensel, E. Motta, S. Decker, and Z. Zdrahal, “Using ontologies for defining tasks, problem-solving methods and their mappings,” Knowledge Acquisition, Modeling and Management, Proceedings of the 10th European workshop, EKAW’97, Lecture Notes in Artificial Intelligence, Springer, Berlin, 1319, 113-128, 1997. [17] H. Akkermans, B. Wielinga, and G. Schreiber, 'Steps in Constructing Problem Solving Methods,' in Knowledge Acquisition for Knowledge-Based Systems, 7th European Workshop, EKAW93, (Toulouse and Caylus, France), Lecture Notes in AI, no 723, Springer-Verlag, Berlin, September 6-10, 1993. [18] H. Eriksson, Y. Shahar, S. W. Tu, A. R. Puerta, and M. A. Musen, “Task Modeling with Reusable Problem-Solving Methods,” Artificial Intelligence, 79(2), pp. 293-326, 1995. [19] L. Steels,”Components of Expertise,” AI Magazine, 11(2), 1990. [20] J. Lee, H. Suh and S. H. Han,” Ontology-based knowledge framework for product development,” Computer-Aided Design and Applications, Vol 2, No. 5, pp635-643, 2005. [21] S. J. Hsu, “Design of an Enabling Mechanism for Effective Yield Analysis Procedure,” Electrical Engineering Department, National Taiwan University, 2007. [22] F. H. Su, “Knowledge Engineering for Semiconductor Yield Analysis: Tool Application and Fault Symptom Identification,” Electrical Engineering Department, National Taiwan University, 2008. [23] S.-F Lau and F.-L Chen, “A Data Clustering Model for Wafer Yield Loss in Semiconductor Manufacturing”, Journal of the Chinese Institute of Industrial Engineers, vol. 21, No. 4, pp. 328-338, 2004. [24] F. H. Su, S. C. Chang, C. Y. Lu, C. M. Fan, J. R. Lee, “Extracting Fault Symptom Identification Knowledge for Semiconductor Yield Analysis”, 2008. [25] Lin, M., H. Guo, and J. Yin, “Goal description language for semantic web service automatic composition,” In Proceedings of the 2005 Symposium on Applications and the Internet (SAINT'05), Vol. 00, Trento: IEEE Computer Society Press, pp. 190-196,2005. [26] S. Sabade and D.M.H. Walker, 'Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis,' Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems (DFT 02), IEEE Press, pp. 381-389, 2002. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40625 | - |
| dc.description.abstract | 如何快速提昇良率一直是半導體產業最關心的議題，根據此議題本研究主要為探討良率分析流程（Yield Analysis Procedure, YAP）在工程意圖層次（Engineering purpose level）之知識建模（Knowledge modeling），以促進良率分析流程知識的分享與重複使用進而提高良率分析流程的績效。由於先前相關的研究在良率分析流程的建模上並未考量工程師執行良率分析的目的（Goal）以及在良率分析流程中所發生的不同情況（Situation），因此本論文的核心著重在於如何建立一個符合工程師思維的良率分析流程知識模型，來支持以條件為基礎的良率分析流程情況判斷（Situation assessment）和意圖路徑控制（Routing controls），進而達成不同的良率分析流程目的。
本研究所提出的良率分析流程建模架構，主要採用知識取得與文件結構化（Knowledge Acquisition and Documentation Structuring, KADS） 的方法並且結合問題解決方法（Problem Solving Methods, PSMs）與本體論工程（Ontology engineering）等方法。提出的模型架構分為三個不同的層次：意圖層（Purpose layer）、意圖連結規則層（Purpose-Link Rule layer）以及知識資源層（Knowledge Resource layer）。 在意圖層的建模上，我們提出了複合意圖（Composite purpose）的觀念與徐仕杰（2007）所提出的原子意圖（Atomic purpose）作區別。複合意圖不僅包括了本身該有的輸入以及輸出的資料描述，還包括啟動該複合意圖的起始條件（Pre-condition）與結束條件（Terminating-condition）。藉由複合意圖的起始條件與良率分析流程的狀態比對，我們可以決定該複合意圖是否被驅動。反之，複合意圖的結束條件則可以用來判斷工程師的目的是否被達成。此外，帶有特定目的的複合意圖也可以更進一步的被拆解成幾個子意圖與相對應的子目的，而本研究進一步提出意圖連結規則（Purpose-link rule）來表達在不同情況下各個子意圖之間的關係。 為了減少一般自然語言所可能帶來的模稜兩可和誤解，我們提出了統一資源模型（Unified resource modeling）來描述所有在良率分析流程中所介紹過的分析意圖、意圖連結規則以及不同的良率分析情況，以利由電腦執行運算。為了希望所建立的統一資源模型可以涵蓋較廣範圍的良率分析流程知識，除了徐仕杰（2007）所提出的半導體領域資料的知識外，我們所建立的統一資源模型還包括了在良率分析流程中所使用的統計工具知識以及一般資料的知識。 我們設計了一個機制來有效地整合與串連所提出的三層結構模型，其中包含五個重要概念：輸出輸入資料集（I/O Dataset）、輸出輸入徵狀（I/O Symptom）、良率分析情況（YAP Situation）、良率分析意圖（YAP Purpose）、良率分析意圖連結規則（YAP Purpose-Link Rule），與四個串連整合步驟：(1)首先先將良率分析工具之輸入輸出資料集轉換成可一般理解之徵狀，(2)然後透過轉換後的徵狀紀錄在所提出的良率分析流程狀態內以敘述工程師目前所掌握的分析狀況，(3)接著藉由所定義之良率分析意圖找出該對應之進入意圖前提條件與結束條件，(4)最後則根據不同良率分析流程狀態的內容靠良率分析意圖連結規則動態規劃出下一個合適的分析意圖。 根據所提出的三層結構模型，我們採用由上而下的（top-down）、反覆的（iterative）以及遞增的（incremental）建模方法來從實務資訊中取得良率分析流程的知識。由上而下的建模方法是為了要確保在意圖層次的良率分析流程知識建模可以符合工程師實際的想法，另一方面也是為了避免良率分析流程的知識建模僅只在系統相依的操作層次。在良率分析流程的知識建模上，我們首先參考半導體廠內良率分析的標準作業程序（Yield analysis standard operating procedure）作為初步的知識來源，而對於後續的知識建模我們則是藉由半導體廠內的實際案例分析，以及來自經驗豐富的工程師寶貴建議，反覆地擴增現有的知識內容，同時也進一步的測試我們所提出的結構模型的彈性與適用性。 | zh_TW |
| dc.description.abstract | Recognizing the importance of rapid yield ramp-up in semiconductor manufacturing industry, this thesis studies the modeling of yield analysis procedure (YAP) knowledge at purpose level to enable knowledge sharing and reuse among engineers for better YAP performance. As compared to former researches without considering engineer’s analysis goals and various situations involved in YAP, this thesis aims at modeling the YAP knowledge to support YAP situation assessments and routing controls for resembling engineer’s behaviors on reaching specific goals.
A framework applying the KADS (Knowledge Acquisition and Documentation Structuring) methodology and integrating both PSMs (Problem Solving Methods) and ontology engineering techniques for modeling YAP knowledge is proposed. The proposed framework contains three layers: Purpose, Purpose-Link Rule, and Knowledge Resource. For modeling of analysis purposes, the concept of composite purpose is proposed to differentiate the atomic purpose modeled by former researches. In specific, a composite purpose is not only described by its input/output data but also characterized by its pre-condition and terminating-condition. A pre-condition specifies the YAP status that a composite purpose should be triggered while a terminating-condition specifies the goal status that a composite purpose should be achieved. A composite purpose with specific goal will be further decomposed into sub-purposes and corresponding sub-goals. To facilitate the dynamic control of sub-purpose routings, the associations between current YAP situations and succeeding sub-purposes are represented as purpose-link rules in IF-THEN format. To reduce the ambiguity and misunderstanding in nature languages, all the wordings (resources) involved in YAP purposes, purpose-link rules, and situations (status) are further modeled and integrated as a unified resource structure so that they can be manipulated by computer programs. In the unified resource structure, in addition to the knowledge of domain data names specified by former researches, both the key words about applying statistics tools and common knowledge are formally specified for the comprehensive modeling of YAP knowledge. Besides, a mechanism with four steps is designed to integrate the proposed three layers, which contains five key concepts of YAP knowledge from function level to purpose level: I/O Dataset, I/O Symptom, YAP Situation, YAP Purpose and YAP Purpose-Link Rule. And the four steps are used to link them together, which are: (1) I/O Symptom Transfer used to transfer I/O dataset of analysis tool into comprehensible I/O symptom, (2) YAP Situation Formalization used to describe YAP status that indicates what engineer has confirmed or suspect based on the current finding symptoms, (3) YAP Purpose Definition directs the course of pre-condition toward a specific goal, and (4) YAP Purpose-Link Rule Definition represents the association between the purposes with respect to various situations. Based on the proposed three-layered framework, the acquisition of YAP knowledge adopts top-down, iterative and incremental modeling approach. The top-down modeling is to align of YAP knowledge model with engineer’s thinking at purpose level while avoiding to be mired in modeling at system-dependent operational level. In specific, the top-down yield analysis Standard Operating Procedure (SOP) from a foundry serves as the knowledge source for the first modeling iteration. With real case studies and additional inputs from veteran engineers, follow-up modeling iterations are then incrementally conducted to test the flexibility and applicability of the proposed framework for YAP knowledge modeling. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T16:53:43Z (GMT). No. of bitstreams: 1 ntu-97-R95546004-1.pdf: 4000361 bytes, checksum: c4f4e61fab536be983a7e2c2ad1fcf64 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iv Contents vi List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Importance of Rapid Yield Ramp-up 1 1.2 Literature Survey 4 1.3 Research Scope and Methodologies 10 1.4 Thesis Organization 13 Chapter 2 Problems & Requirements of YAP 14 2.1 Introduction of Semiconductor Manufacturing Data 14 2.2 EDA Function & Analysis purpose 16 2.3 Current enabling mechanism: Purpose Planning Tree 19 2.4 Problems & Requirements of YAP 20 Chapter 3 Knowledge framework with simple example 24 3.1 Introduction of Knowledge Framework 24 3.2 Design and Analysis of Modeling Procedure 27 3.3 Purpose Modeling 31 3.4 Control Strategy Modeling 34 3.5 Knowledge Resource Modeling 37 Chapter 4 Knowledge Framework Applied in Semiconductor YAP 45 4.1 Scenario Example Descriptions of Semiconductor Manufacturing 46 4.2 YAP knowledge modeling based on Yield Analysis SOP 48 4.2.1 YPA Analysis Purpose Definition and Modeling 48 4.2.2 Control Strategy Definition and Modeling 52 4.3 Knowledge abstraction of YAP analysis purpose & control strategy 59 4.3.1 Knowledge Abstraction from Purpose Modeling 60 4.3.2 Knowledge Abstraction from Purpose Link Rule Modeling 66 Chapter 5 Extendibility and Maintainable of Knowledge Framework 69 5.1 Introduction of Actual Scenario Example in Semiconductor Practices 70 5.2 Purpose Modeling of Actual Scenario Example 71 5.3 Control Strategy Modeling of Actual Scenario Example 73 5.4 Extendibility and Maintainability of Knowledge Resource 74 Chapter 6 Conclusions and Further Work 77 Reference 80 | |
| dc.language.iso | en | |
| dc.subject | 良率分析流程 | zh_TW |
| dc.subject | 知識工程 | zh_TW |
| dc.subject | 知識建模 | zh_TW |
| dc.subject | 工程意圖 | zh_TW |
| dc.subject | Knowledge Modeling | en |
| dc.subject | Knowledge Engineering | en |
| dc.subject | Engineering Purpose | en |
| dc.subject | Yield Analysis Procedure(YAP) | en |
| dc.title | 良率分析流程在工程意圖層次之知識建模 | zh_TW |
| dc.title | Modeling of Yield Analysis Procedure (YAP) Knowledge at Engineering Purpose Level | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 范治民 | |
| dc.contributor.oralexamcommittee | 蔡雅蓉,鄭秀杰,高慶斌 | |
| dc.subject.keyword | 知識工程,良率分析流程,知識建模,工程意圖, | zh_TW |
| dc.subject.keyword | Knowledge Engineering,Yield Analysis Procedure(YAP),Knowledge Modeling,Engineering Purpose, | en |
| dc.relation.page | 82 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-30 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 工業工程學研究所 | zh_TW |
| 顯示於系所單位： | 工業工程學研究所 | |
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