一個操作在1.2伏特之十位元高速管線式類比數位轉換器

Abstract

本論文闡述一個操作在1.2伏特的十位元雙通道時間交錯式之管線式類比數位轉換器，並以台積電0.13-μm CMOS製程製作。為達到高度的轉換速率，於第一級MDAC內將餘數放大的動作做分解以增加其回授係數。為了減少不匹配所帶來的效應，運算放大器的共用技巧被運用在兩個通道間，以及所提出的時脈產生器被設計用來抑止取樣時間的不匹配。 依據量測的結果，本晶片操作在50MS/s的取樣頻率下，DNL為-0.49/+0.43LSB，INL為-1.05/+0.86LSB，對於1MS/s的信號輸入頻率，在50MS/s的取樣頻率下，SNDR為56.53dB，SFDR為68.38dB，當時脈升至250MS/s時，SNDR與SFDR分別降為37.63dB與41.61dB。在250MS/s的轉換速率下，功率消耗為 106mW。晶片總面積占1.3mm2。 在第一章中，將介紹管線式類比數位轉換器的架構。第二章討論時間交錯式類比數位轉換器系統下其通道間的不匹配所帶來的效應。第三章說明所提出來的新架構，用來增進轉換速度以及減少不匹配的效應。電路細節與模擬結果包含在第四章。第五章呈現量測的設定與量測結果，最後於第六章中對這個電路做總結。

This thesis presents a 1.2V 10-bit CMOS two-channel time-interleaved pipelined ADC in a standard 0.13-μm CMOS process. For high conversion speed, the first stage with divided residue gain is proposed to increase the feedback factor of the MDAC. In order to reduce the mismatch-effects, opamp-sharing technique is applied between two channels, and the proposed clock generator is designed to suppress the sampling-time mismatch. According to the measurement results, the prototype ADC exhibits a DNL of -0.49/+0.43LSB and an INL of -1.05/+0.86LSB at the sampling rate of 50MS/s. For 1MHz input frequency, the SNDR and SFDR achieve 56.53dB and 68.38dB at 50MS/s. The SNDR and SFDR are reduced to 37.63dB and 41.61dB at 250MS/s for 1MHz input. The power consumption is 106mW at the conversion rate of 250MS/s. The chip with pads occupies 1.3mm2. Chapter 1 introduces the pipelined ADC architecture. Chapter 2 discusses the channel mismatch effects in the time-interleaved ADC system. A proposed architecture to increase conversion speed and to reduce mismatch effects is given in Chapter 3. Detail circuit implementation and simulation result are shown in Chapter 4. Chapter 5 presents the test setup and measurement results. Finally, conclusions are summarized in Chapter 6.