多重供應電壓平面規劃與電源網路之同步合成

Abstract

隨著製程的縮小，電壓降在先進積體電路設計中已成為非常重要的議題。由於傳統的電壓降分析方式相當耗時，傳統分析方式並不適合應用在平面規劃與電源供應網的同步共同合成上。在另一方面，多重供應電壓設計使得電源供應網路上電壓降分析變得更加複雜。因此，在這篇論文中，我們首先提出一個十分有效率並且合理的電壓降模型。基於我們所提出的電壓降模型，針對使用多重電壓的電路設計，我們設計出一個非常有效且快速的平面規劃演算法。更明確地說，我們的演算法包含了一個以最小化平面周長為目標的平面擺放器，一個線性時間的電路區塊相鄰圖建造器以及一個電壓島群集器。在平面規劃完之後，基於使用線性規劃技巧的基礎上，我們提出一套可以同時擺放電源供應墊以及重新分布空白區域的演算法去進一步降低電壓降效應。實驗結果驗證了我們所提出的電壓降模型也顯示我們的演算法可以大量加速平面規劃的收斂速度並且有效降低電壓降效應。

With technology scaling, the voltage (IR) drop in the power/ground (P/G) network becomes a crucial problem in modern IC designs. Since traditional IR-drop analysis methods are often very time-consuming, it is not feasible to apply traditional IR-drop analysis methods to co-synthesize the P/G network and floorplans. On the other hand, multiple-supply-voltage (MSV) designs further complicate the IR-drop analysis in the P/G network. Therefore, in this thesis, we first propose an efficient, yet reasonable IR-drop model. Based on the proposed IR-drop model, we present an efficient and effective floorplanning algorithm considering the IR-drop effect and the P/G network routing resource for designs with wire-bonding packaged power networks. Specifically, a perimeter-driven floorplanner, a linear-time block-adjacency-graph constructor, and a voltage-island clustering technique are presented. After floorplanning, we develop a linear programming based algorithm to perform simultaneous power-pad placement and whitespace redistribution for the IR-drop reduction. Experimental results validate the proposed IR-drop model and show that our algorithms can significantly improve the floorplanning convergence and effectively reduce the IR-drop cost for MSV designs.