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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39481Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Cheng-Jiun Dai | en |
| dc.contributor.author | 戴承雋 | zh_TW |
| dc.date.accessioned | 2021-06-13T17:29:35Z | - |
| dc.date.available | 2016-07-25 | |
| dc.date.copyright | 2011-07-25 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-07-13 | |
| dc.identifier.citation | [1] J.B. Kuo, J. Lou, 'Low-Voltage CMOS VLSI Circuits,' Wiley, New York,1999.
[2] G.E. Moore, 'Progress inDigital Integrated Electronics, ' International Electron Devices Meeting, Vol. 21,pp. 11-13, 1975 [3] blindspot, digital, emerging issues, technology by thenextwavefutures on 2 August,2009 [4] ITRS, 'ITRS 2010 Update Documents for Review,' http://www.itrs.net/Links/2010ITRS/Home2010.htm. [5] D. Samanta, A. Pal, 'Optimal Dual-VT Assignment for Low-voltage Energy-Constrained CMOS Circuits,' International Conference on VLSIDesign, pp. 193-198, Jan 2002. [6] ITRS,“ITRS 2001 Documents for Review http://www.itrs.net/Links/2001UTRS/Home.htm [7] Nam SungKimTodd AustinDavidBlaauwTrevorMudg“Leakage Current:Moore’s Law MeetsStatic Power”, IEEE Computer Society ,December 2003 [8] T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H.Inokawa, and T. Tsuchiya, “A 0.5V MTCMOS/SIMOX LogicGate,'IEEE J. Solid-State Circuits, Vol. 32, No. 10, pp. 1604-1609, 1997 [9] S. Shigematsu, S. Muthoh, Y. Matsuya, Y.Tanabe, and J. Yamada, “ A 1V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits,' IEEE J. Solid-State Circuits, Vol. 32, No. 6, pp. 861-869, 1997 [10] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,' IEEE Trans. Electron Devices, Vol. 44, No. 3, pp. 414-422, 1997 [11] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, “Channel Profile Optimization and Device Design for Low-PowerHigh-Performance Dynamic- Threshold MOSFET,' IEDM Digest, pp. 113-116, 1996. [12] Synopsys, 'Design Compiler User Guide,' ~2007.03 [13] Synopsys, 'PrimeTime User Guide,' ~2007.06. [14] Synopsys, 'PrimePower User Guide,' ~2007.06. [15] Cadence, 'SoC Encounter User Guide,' ~2007.06. [16] 'Power Compiler User Guide,'2007,03. [17] S. Mukhopadhyay, K. Roy, 'Leakage Estimation and Leakage Control forNano-Scale CMOS Circuits,' Design Automation Conference, 2004. [18] J .B. Kuo, 'CMOS Digital IC,' McGraw-Hill, Taiwan, 1996. [19] R.X. Gu, M.I. Elmasry, 'Power dissipation analysis and optimization of deep submicron CMOS digital circuits,' IEEE Journal of Solid-state Circuits, Vol. 31, lssue 5, pp. 707-71 3, May 1996. [20] J. B. Kuo,“Low-Voltage SOI CMOS Devices and Circuits,' Wiley, New York, 2004. [21] Usami, K., Kawabe, N., Koizuki, M., Seta, K., Furusawa, T.“AutomatedSelective Multi-Threshold Design for Ultra-Low Standby Applications,'Low Power Electronics and Design ConfProc, pp. 202-206, 2002. [22] Kao, J., Narendra, S., Chandrakasan, A.“MTCNMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Pattern,'Design Automation Conf. Proc, pp. 495-500, 1998. [23] B. Chung and J.B. Kuo, 'Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application” [24] Shen, E, Kuo, J. B.“A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques.' IEEE ConfElecDevand Solid State Ckts, pp. 243-245, 2003. [25] Shen, E, Kuo, J. B.“0.8V CMOS CAM Cell Circuit with a Fast Tag-Compare Capability Using Bulk PMOS Dynamic-Threshold (BP-DTMOS) Technique Based on Standard CMOS Technology for Low-Voltage VLSI Systems,' IEEE International Symp. Circuits and Systems Proc, IV 583-586, 2002. [26] C. H. Lin and J. B. Kuo, “Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique,” Power and Timing Optimization Symposium, Delft, Netherlands, Sept. 2009 [27] C. H. Lin and J. B. Kuo, “Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique,” Power and Timing Optimization Symposium, Delft, Netherlands, Sept. 2009 [28] C. H. Lin and J. B. Kuo, “Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique,” Power and Timing Optimization Symposium, Delft, Netherlands, Sept. 2009 [29] C. H. Lin and J. B. Kuo, “Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique,” Power and Timing Optimization Symposium, Delft, Netherlands, Sept. 2009 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39481 | - |
| dc.description.abstract | 這篇論文敘述實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用。首先在第一章中先介紹半導體元件以及積體電路在SOC上的低電壓低功率消耗的趨勢。接著在第二章中介紹使用多重臨限電壓和動態臨限電壓技術的基體互補式金氧半動態臨限電壓元件，接下來使用電子設計自動化軟體，讓基體互補式金氧半動態臨限電壓元件設計系統單晶片。第三章藉由16位元的乘法器介紹使用基體互補式金氧半動態臨限電壓元件設計系統單晶片的後段設計中測試和分析，以及相關驗證程序。 | zh_TW |
| dc.description.abstract | The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T17:29:35Z (GMT). No. of bitstreams: 1 ntu-100-R98943101-1.pdf: 2994998 bytes, checksum: 935cc116e8d31c1cc48611519b8ff319 (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 口試委員審定書..................... i
致謝................................ii 中文摘要...........................iii ABSTRACT............................iv 目錄.................................v 圖目錄..............................vii 表目錄..............................ix Chapter 1 導論.......................1 1.1矽互補式金氧半超大型積體電路的演化及發展趨勢.........1 1.2數位積體電路設計中EDA技術..........7 1.3電路的功率消耗分析....................10 1.4研究目標與論文架構....................13 Chapter 2 0.8V Bulk PMOS動態臨限電壓技術使用雙臨界電壓系統電路分析..14 2.1多重臨界電壓與動態臨限電壓技術....14 2.2 Bulk PMOS 動態臨限電壓矽金氧半元件技術.............16 2.3 Bulk PMOS 動態臨限矽金氧半元件邏輯閘電路...........19 2.4電子設計自動化......................23 2.4.1從Gate Level Netlist到自動佈局及繞線.............23 2.4.2使用BP-DTMOS-DT邏輯閘佈局以及繞線................25 Chapter 3 0.8V Bulk PMOS DTMOS 技術後段設計功率消耗分析以及驗證...........................................32 3.1功率消耗分析..............................32 3.2 DRC 與 LVS...............................37 Chapter 4 結論與未來研究方向...................42 參考文獻.......................................44 | |
| dc.language.iso | zh-TW | |
| dc.subject | 金氧半動態臨限電壓技術 | zh_TW |
| dc.subject | 電子設計自動化 | zh_TW |
| dc.subject | DTMOS | en |
| dc.subject | Electronic Design Automation | en |
| dc.title | 實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用 | zh_TW |
| dc.title | Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 葉正信,陳正雄 | |
| dc.subject.keyword | 電子設計自動化,金氧半動態臨限電壓技術, | zh_TW |
| dc.subject.keyword | Electronic Design Automation,DTMOS, | en |
| dc.relation.page | 46 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-07-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-100-1.pdf Restricted Access | 2.92 MB | Adobe PDF |
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