請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39243
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林浩雄(Hao-Hsiung Lin) | |
dc.contributor.author | Wen-Ting Chu | en |
dc.contributor.author | 朱文定 | zh_TW |
dc.date.accessioned | 2021-06-13T17:24:45Z | - |
dc.date.available | 2006-02-02 | |
dc.date.copyright | 2005-02-02 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-01-26 | |
dc.identifier.citation | [1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol 46, p. 1288, 1967.
[2] Dataquest, May 2004. [3] “Worldwide flash card market forcast,” Dataquest, 2004. [4] “WSTS semiconductor forecast,” WSTS, 2004. [5] Dov Frohman-Bentchkowsky, “A fully decoded 2048-bit electrically programmable FAMOS read-only memory,” IEEE J. Solid-State Circuits, VOL. SC-6, pp. 301-306, October 1971. [6] Murray H. Woods, “An E-PROM’s integrity starts with its cell structure,” Electronic Magazine, August 1980. [7] F. Masuoka, et al., “A new flash EEPROM cell using triple poly-Si technology,” IEEE IEDM Tech. Dig., pp. 464-467, 1984 [8] K.-C. Huang, Y.-K. Fang, D.-N. Yaung, C.-W. Chen, H.-C. Sung, D.-S. Kuo, Chung S. Wang, “The impacts of control gate voltage on the cycling endurance of split gate flash memory,” IEEE Electron Device Lett., VOL. 21, pp. 359-361, July 2000. [9] B. Yeh, “Single transistor non-volatile electrically alterable semiconductor memory device,” US Patent 5029130, 1991. [10] S. Kianian, A. Levi, D. Lee, and Y.-W.Hu, “A novel 3 volts-only, small sector erase, high density Flash E2PROM,” in Symp. VLSI Technol. Dig., 1994, pp. 71-72. [11] K. Naruke, S. Yamada, E. Obi, S. Taguchi, and M. Wada, “A new flash-erase EEPROM cell with a select-gate on its source side,” in IEDM Tech. Dig., 1989, pp. 603-606. [12] G. Bersuker, Y. Jeon, G. Gale, J. Guan, H.R. Huff, “Modeling trap generation process in thin oxides,” in IRW, 2000, pp. 107-111. [13] C.-H. Wang, M. Hemming, P.Klinger, Albert V. Kordesch, C.-M. Liu, Ken Su, “On the cell misalignment for multilevel storage FLASH E2PROM,” in Symp. VLSI Technol. Dig., 1999, pp. 191-194. [14] Jack ZZ. Peng, Sameer Haddad, Hao Fang, Chi Chang, Steve Longcor, Bernard Ho, Yu Sun, David Liu, Yuan Tang, James Hsu, Shengwen Luan, Jih Lien, “Flash EPROM endurance simulation using physics-based models,” in IEDM Tech. Dig., 1994, pp. 295-298. [15] John M. Caywood, Chih-Jen Huang, and Y. J. Chang, “A Novel Nonvolatile Memory Cell Suitable for Both Flash and Byte-Writable Applications,” IEEE Trans. Electron Devices, VOL. 49, pp. 802-807, May 2002. [16] Takeshi Nakayama, Yoshikazu Miyawaki, Kazuo Kobayashi, Yasushi Terada, Hideaki Arima, Takayuki Matsukawa, and Tsutomu Yoshihara, “A 5-V-Only One-Transistor 256K EEPROM with Page-Mode Erase,” IEEE Journal of Solid-State Circuits, VOL. 24, pp. 911-915, August 1989 [17] T. C. Ong, A. Fazio, N. Mielke, S. Pan, N. Righos, G. Atwood, and S. Lai, “Erratic erase in ETOX flash memory array,” in VLSI Tech. Dig., 1993, pp. 83-84. [18] John Van Houdt, Paul Heremans, Ludo Deferm, Guido Groeseneken, and Herman E. Maes, “Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications,” IEEE Trans. Electron Devices, VOL. 39, pp. 1150-1156, May 1992. [19] Y. Ma, C. S. Pang, J. Pathak, S.C. Tsao, C. F. Chang, Y. Yamauchi, and M. Yoshimi, “A novel high density contactless flash memory array using split-gate source-side-injection cell for 5V-only applications,” in Symp. VLSI Technol. Dig., 1994, pp. 49-50. [20] Kung-Hong Lee and Ya-Chin King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded nonvolatile memory applications,” in Symp. VLSI Technol. Dig., 2003, pp. 93-94. [21] Albert Bergemont, Hosam Haggag, Mike Hart, and Larry Anderson, “A new cell and process for very high density full feature EEPROMs and low power applications,” in Symp. VLSI Technol. Dig., 1993, pp. 152-155. [22] N. Ajika, M. Ohi, T. Futatsuya, H. Arima, T. Matsukawa, and N. Tsubouchi, “A novel cell structure for 4M bit full feature EEPROM and beyond,” IEDM Tech. Dig., 1991, pp. 295-298. [23] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakibara, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, “Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for flash memory with a P-channel cell,” IEDM Tech. Dig., 1995, pp. 279-282. [24] C.C.-H. Hsu, A. Acovic, L. Dori, B. Wu, T. Lii, D. Quinlan, D. DiMaria, Y. Taur, M. Wordeman, and T. Ning, “A high speed, low power P-channel flash EEPROM using silicon rich oxide as tunneling dielectric,” Ex. Abstracts of SSDM, 1992, p. 140. [25] Steve S. Chung, S. N. Kuo, C. M. Yih, and T. S. Chao, “Performance and reliability evaluations of P-channel flash memories with different programming schemes,” IEDM Tech. Dig., 1997, pp. 295-298. [26] T. Ohnakado, H. Onoda, O. Sakamoto, K. Hayashi, N. Nishioka, H. Takada, K. Sugahara, N. Ajika, and S. Satoh, “Device characteristics of 0.35 mm p-channel DINOR flash memory using band-to-band tunneling-induced hot electrons (BBHE) programming,” in IEEE Trans. Electron Devices, vol. 46, 1999, pp. 1866-1871. [27] Frank Ruei-Ling Lin, and Charles Ching-Hsiang Hsu, “New divided-source structure to eliminate instability of threshold voltage in P-channel flash memory using channel hot-hole-induced-hot-electron programming,” in Symp. VLSI Technol. Dig., 1999, pp. 203-206. [28] Yu-Lin Chu, and Ching-Yuan Wu, “A new observation of band-to-band tunneling induced hot carrier stress using charge-pumping technique,” IEEE Electron Device Lett., VOL. 21, pp. 123-126, March 2000. [29] N. Ajika, M. Ohi, H. Arima, T. Matsukawa, and N. Tsubouchi, “Enhanced reliability of native oxide free capacitor dielectrics on rapid thermal nitrided polysilicon,” in Symp. VLSI Technol. Dig., 1991, pp. 63-64. [30] Rebecca Mih, Jay Harrington, Kevin Houlihan, Hyun Koo Lee, Kevin Chan, Jeffrey Johnson, Bomy Chen, Jiang Yan, Andreas Schmidt, Christian Gruensfelder, Kisang Kim, Danny Shum, Connie Lo, Dana Lee, Amitay Levi, and Chung Lam, “0.18mm Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” in Symp. VLSI Technol. Dig., 2000, pp. 120-121. [31] Jan Van Houdt, Paul Heremans, Ludo Deferm, Guido Groeseneken, and Herman E. Maes, “Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful EEPROM Applications,” IEEE Trans. Electron Device, VOL. 39, pp. 1150-1156, May. 1992. [32] Surya Bhattacharya, Kafai Lai, Karen Fox, Peter Chan, Eugene Worley, and Umesh Sharma, “Improved Performance and Reliability of Split Gate Source-Side Injected Flash Memory Cells,” IEDM Tech. Dig., 1996, pp. 339-342. [33] Tung-Ming Pan, Tan-Fu Lei, Wen-Luh Yang, Chun-Ming Cheng, and Tien-Sheng Chao, “High quality interpoly-oxynitride grown by NH3 nitridation and N2O RTA treatment,” IEEE Electron Device Lett., VOL. 22, pp. 68-70, February 2001. [34] Huang-Chung Cheng, Fang-Shing Wang, and Chun-Yao Huang, “Effects of NH3 plasma passivation on N-channel polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Device, VOL. 44, pp. 64-68, January. 1997. [35] S. C. Song, H. F. Luan, C. H. Lee, A. Y. Mao, S. J. Lee, J. Gelpey, S. Marcus, and D. L. Kwong, “Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3-nitrided Si,” in Symp. VLSI Technol. Dig., 1999, pp. 137-138. [36] H. C. Cheng, H.W. Liu, H. P. Su, and G. Hong, “Superior low-pressure-oxidized Si3N4 films on rapid-thermal-nitrided poly-Si for high-density DRAM’s,” IEEE Electron Device Lett., VOL. 22, pp. 68-70, February 2001. [37] Rudu Vancu, Ling Chen, Ray Lin Wan, Tam Nguyen, Woo-Ping Lai, Kam-Fai Tang, Andrei Mihnea, Alan Renninger, and George Smarandoiu, “A 35ns CMOS EEPROM with Error correcting circuitry,” in ISSCC Dig. Tech. Paper, 1990, pp. 64-65. [38] Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, and Tsutomu Yoshihara, “120-ns 128K X 8-bit/64K X 16-bit CMOS EEPROM’s,” in IEEE Journal of Solid-State Circuits, vol. 24, 1989, pp. 1244-1249. [39] Stefano Gregori, Alessandro Cabrini, Osama Khouri, and Guido Torelli, “On-chip error correcting techniques for new-generation flash memories,” in Proceedings of THE IEEE, vol. 91, 2003, pp. 602-616 [40] J. Caywood, and G. Derbenwick, “Nonvolatile memory,” in ULSI devices, C. Y. Chang and S. M. Sze, Eds. New York: Wiley, 2000, pp. 377-473. [41] C. J. Huang, Y. C Liu, S. F. Hong, A. Wu, M. C. Wang, S. Hsu, L. C. Hsia, Y. J. Chang, Y. T. Lo, and F.-T. Liu, “A novel P-channel flash EEPROM cell with simple process and low power consumption,” in Proc. SSDM, 2000, pp. 278-279. [42] Min She, Tsu-Jae King, Chenming Hu, Wenjuan Zhu, Zhijiong Luo, Jin-Ping Han, and Tso-Ping Ma, “JVD silicon nitride as tunnel dielectric in p-channel flash memory,” IEEE Electron Device Lett., VOL. 23, pp. 91-93, February 2002. [43] Ruei-Ling Lin, Ted Chang, Alex C. Wang, and Charles Ching-Hsiang Hsu, “New self-adjusted dynamic source multilevel p-channel flash memory,” IEEE Trans. Electron Device, VOL. 47, pp. 841-847, April 2000. [44] Kuo-Feng You, and Ching-Yuan Wu, “A new Quasi-2-D model for hot-carrier band-to-band tunneling current,” IEEE Trans. Electron Device, VOL. 46, pp. 1174-1179, June 1999. [45] S. J. Shen, C. S. Yang, Y. S. Wang, and C. C.-H. Hsu, “Novel self-convergent programming scheme for multi-level p-channel flash memory,” IEDM Tech. Dig., 1997, pp. 287-290. [46] Jong T. Park, Jeoung Y. Chun, Han K. Kim, Sung J. Jang, and Chong G. Yu, “New programming and erasing schemes for p-channel flash memory,” IEEE Electron Device Lett., VOL. 21, pp. 491-493, October 2000. [47] Takahiro Ohnakado, and Shin-ichi Satoh, “Novel self-limiting high-speed program scheme of p-channel DINOR flash memory with n-channel select transistors,” IEEE Trans. Electron Device, VOL. 47, pp. 1209-1213, June 2000. [48] O. Sakamoto, H. Onoda, T. Katayama, K. Hayashi, N. Yamasaki, K. Sakakibara, T. Ohnakado, H. Takada, N. Tsuji, N. Ajika, M. Hatanaka, and H. Miyoshi, “A high programming throughput 0.35 mm p-channel DINOR flash memory,” in Symp. VLSI Technol. Dig., 1996, pp. 222-223. [49] S. S. Chung, S. T. Liaw, C. M. Yih, Z. H. Ho, C. J. Lin, D. S. Kuo, and M. S. Liang, “N-channel versus p-channel flash EEPROM-which one has better reliabilities,” in Proc. IRPS, 2001, pp. 67-72. [50] Hon-Sum Wong, “Gate current injection in MOSFET’s with a split-gate (virtual drain) structure,” IEEE Electron Device Lett., VOL. 14, pp. 262-264, May 1993. [51] Cheng-Yuan Hsu, Chi-Wei Hung, Da Sung, Chi-Shan Wu, S. C. Chen, H. H. Kuo, J. Y. Pan, C. L. Chen, I. C. Chuang, Vincent Huang, C. C. Hsue, Der-Tsyr Fan, Jung-Chang Lu, Caleb Y.-S. Cho, Kevin Tseng, Annie Hsu, Ben Sheen, Prateep Tuntasood, and Chiou-Feng Chen, “Split-gate NAND flash memory at 120nm technology node featuring fast programming and erase,” in Symp. VLSI Technol. Dig., 2004, pp. 78-79. [52] T. Kobayashi, Y. Sasago, H. Kurata, S. Saeki, Y. Goto, T. Arigane, Y. Okuyama, H. Kume and K. Kimura, “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications,” IEDM Tech. Dig., 2001, pp. 2.2.1-2.2.4. [53] Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, and K. Furusawa, “90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F2 /bit and programming throughput of 10 MB/s,” IEDM Tech. Dig., 2003, pp. 34.2.1-34.2.4. [54] Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., VOL. 21, pp. 543-545, November 2000. [55] M. Specht, U. Dorda, L. Dreeskornfeld, J. Kretz, F. Hofmann, M. Städele, R. J. Luyken, W. Rösner, H. Reisinger, E. Landgraf, T. Schulz, J. Hartwich, R. Kömmling, and L. Risch, “20 nm tri-gate SONOS memory cells with multi-level operation,” IEDM Tech. Dig., 2004, pp. 1084-1087. [56] C. Monzio Compagnoni, D. Ielmini, A. S. Spinelli, A. L. Lacaita, C. Previtali, and C. Gerardi, “Study of data retention for nanocrystal flash memories,” in Proc. IRPS, 2003, pp. 506-512. [57] J. De Blauwe, “Nanocrystal nonvolatile memory devices,” in IEEE Trans. Nanotechnology, VOL. 1, pp. 72-77, 2002. [58] J. H. Park, H. J. Joo, S. K. Kang, Y. M. Kang, H. S. Rhie, B. J. Koo, S. Y. Lee, B. J. Bae, J. E. Lim, H. S. Jeong, and Kinam Kim, “Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct Via technology and robust 100 nm thick MOCVD PZT technology,” IEDM Tech. Dig., 2004, pp. 591-594. [59] H. J. Joo, Y. J. Song, H. H. Kim, S. K. Kang, J. H. park, Y. M. Kang, E. Y. Kang, S. Y. Lee, H. S. Jeong, and Kinam Kim, “Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies,” in Symp. VLSI Technol. Dig., 2004, pp. 148-149. [60] S. Ueno, T. Eimori, T. Kuroiwa, H. Furuta, J. Tsuchimoto, S. Maejima, S. Iida, H. Ohshita, S. Hasegawa, S. Hirano, T. Yamaguchi, H. Kurisu, A. Yutani, N. Hashikawa, H. Maeda, Y. Ogawa, K. Kawabata, Y. Okumura, T. Tsuji, J. Ohtani, T. Tanizaki, Y. Yamaguchi, T. Ohishi, H. Hidaka, T. Takenaga, S. Beysen, H. Kobayashi, T. Oomori, T. Koga, and Y. Ohji, “A 0.13 µm MRAM with 0.26×0.44µm2 MTJ optimized on universal MR-RA relation for 1.2V high-speed operation beyond 143MHz,” IEDM Tech. Dig., 2004, pp. 579-582. [61] Y. Asao, T. Kajiyama, Y. Fukuzumi, M. Amano, H. Aikawa, T. Ueda, T. Kishi, S. Ikegawa, K. Tsuchida, Y. Iwata, A. Nitayama, K. Shimura, Y. Kato, S. Miura, N. Ishiwata, H. Hada, S. Tahara, and H. Yoda, “Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell,” IEDM Tech. Dig., 2004, pp. 571-574. [62] S. J. Ahn, Y. J. Song, C. W. Jeong, J. M. Shin, Y. Fai, Y. N. Hwang, S. H. Lee, K. C. Ryoo, S. Y. Lee, J. H. Park, H. Horii, Y. H. Ha, J. H. Yi, B. J. Kuh, G. H. Koh, G. T. Jeong, H. S. Jeong, Kinam Kim, and B. I. Ryu, “Highly manufacturable high density phase change memory of 64Mb and beyond,” IEDM Tech. Dig., 2004, pp. 907-910. [63] Stefan Lai, “Current status of phase change memory and its future,” IEDM Tech. Dig., 2003, pp. 10.1.1-10.1.4. [64] R. Sezi, A. Walter, R. Engl, A. Maltenberger, J. Schumann, M. Kund, and C. Dehm, “Organic materials for high density non-volatile memory applications,” IEDM Tech. Dig., 2003, pp. 259-262. [65] Michael N. Kozicki, Chakravarthy Gopalan, Murali Balakrishnan, Mira Park, and Maria Mitkova, “Non-volatile memory based solid electrolytes,” Preceding of NVMTS, 2004. [66] Gerhard Müller, Thomas Happ, Michael Kund, Gill Yong Lee, Nicolas Nagel, and Recai Sezi, “Organic Status and Outlook of Emerging Nonvolatile Memory Technologies,” IEDM Tech. Dig., 2004, pp. 567-570. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39243 | - |
dc.description.abstract | 本研究主題為分離式閘極非揮發性記憶體製程改進及電性分析研究。記憶體中使用一種類似LOCOS的製程可用來產生一個多晶矽尖角,以增強電場,並藉由Fowler-Nordheim (F-N) tunneling作記憶胞(memory cell)抹除(erase)。我們發現穿隧氧化層(tunnel oxide) 電荷捕捉效應,在不同的抹除電壓下,當記憶胞讀取是操作在線性區時,較高的抹除電壓會導致較快的記憶胞電流下跌,也就是說更多的電荷被捕捉到。對浮極(floating gate)接出的元件作F-N tunneling測試時,當跨在氧化層的電場愈高,則愈多的電子被捕捉到。經過250O C烘烤之後,在愈高電壓下氧化層所捕捉到的電荷愈難被釋放出來。
針對full-featured EEPROM,我們提出一種高源極偶合比(coupling ratio)的設計用在分離式閘極記憶胞,其記憶胞面積小於22F2 。一般傳統的記憶胞須要一個選擇電晶體,所以面積無法很小。利用禁止(inhibited)源極電壓加在沒選到的記憶胞,就可達到bit-抹除的功能。此記憶胞擁有很好的抗程式(program)和抹除干擾(disturb)的能力。且可通過300k次程式/抹除耐受度(endurance)測試;而且經過耐受度測試後,此記憶胞會有更好的抗抹除干擾的能力。 此外,我們首先提出一種p型的分離式閘極快閃(flash)記憶胞加入一個多晶矽尖角的結構可降低抹除電壓到12V。我們也評估通道熱電洞撞擊產生熱電子(channel-hot-hole impact ionization induced channel-hot-electrons (CHE))和能隙到能隙穿隧產生的熱電子(band-to-band tunneling induced hot electrons (BBHE))等兩種程式的方法。BBHE 的方法比起用CHE 在注入效率上,大約多了兩個數量級。此記憶胞亦擁有很好的抗程式干擾的能力,而程式干擾是一個主要的問題,在p型的堆疊式閘極記憶胞,此兩種程式方法皆可達到300k次的耐受度測試。 在多晶矽氧化時,鳥嘴(bird’s beak)會伸到氮化矽層下,特別是沿著多晶矽的grain boundary,如此會造成浮極的間距大小不一,甚至會連在一起,如此則記憶胞的面積便無法再縮小。我們提出使用氨氣來氮化多晶矽的表面,可避免鳥嘴連在一起和浮極的間距不均勻;浮極的間距可因此從0.09 mm改善到0.03 mm。由XPS 的分析可發現經過氨氣氮化的多晶矽表面的氧化氮化矽層的厚度小於5 nm。 我們也首先利用0.13 mm 銅製程開發出三重自我對準的分離式閘極快閃記憶胞,自我對準的結構主要是後層對前層的垂直壁做一個spacer。 當記憶胞面積縮小時,由於較大的縱深比,spacer會更容易形成,且形狀更好,長度更易控制。另外此方法所用的製程皆和標準的邏輯製程相容。其字元線的通道長度為0.11 mm,記憶胞的面積小於13F2和堆疊式閘極記憶胞相當。電性分析顯示其程式和抹除的速度皆相當不錯,且可通過300k次的耐受度測試,並有相當好的抗程式干擾的表現。 | zh_TW |
dc.description.abstract | The study presented in this thesis is dedicated to split-gate non-volatile memory process technology improvement and cell characterization. A sharp poly-tip structure, generated by using a LOCOS-like approach is introduced to increase the electric field when the cell is erased using Fowler-Nordheim (F-N) tunneling through poly-poly oxide. The tunnel oxide charge trapping effect under various erase voltages is studied. When reading the cell in the linear region, it was found that the higher the erase voltage applied, the faster the cell current degraded, the greater the likelihood of charges being trapped in the oxide. By observing the F-N tunneling stress on floating gate (FG) connected devices, we also found that the higher the electric field across the oxide, the more the electrons are trapped. After 250O C baking, the oxide trapped charges created by the higher stress voltage are more difficult to heal than those created by a lower stress voltage.
A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22F2 is first proposed in this study. This is in contrast to a traditional cell that requires an extra select-transistor and is not effective for cell size when compared to the new design cell. In this design, an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and has passed a 300k program/erase (P/E) cycling test. It was found that after the P/E cycling stress, the cell gains a better erase disturb immunity. A p-channel split-gate flash memory cell, employing a field-enhanced structure, is also demonstrated in this study. The erase voltage is as low as 12 V. In cell programming, both channel-hot-hole impact ionization induced channel-hot-electrons (CHE) and band-to-band tunneling induced hot electrons (BBHE) are evaluated. BBHE shows an injection efficiency of ~2 orders in magnitude higher than that of CHE. The cell also demonstrated an acceptable program disturb window, which is of high concern in a p-channel stacked-gate cell. Both programming approaches can pass 300k P/E cycles. During poly oxidation, the bird’s beak encroaches under the SiN film, especially along the poly grain boundary, causing non-uniform FG spacing, even bridging, which is an obstacle to cell shrinkage. We proposed an ammonia treatment on the poly to nitridize the poly surface, thereby avoiding bird’s beak bridging. After the ammonia treatment, FG spacing is quite uniform and can be improved from 0.09 mm to 0.03 mm. The XPS analysis on the ammonia treated poly shows the oxynitride thickness is less than 5 nm. A shrinkable triple self-aligned split-gate flash cell fabricated using a 0.13-mm copper interconnect process is firstly demonstrated in this study. The approach used here to create a self-aligned structure is to form a spacer against the prior layer. Due to a higher aspect ratio when the cell pitch decreases, the profile of the spacer structure becomes sharper. This improves process control of the spacer profile and length. All processes used here are compatible with standard logic process. The word line channel length of the cell is 0.11 mm. The cell area is comparable to that of a stacked-gate cell and can be less than 13F2. Characterization shows considerable program and erase speed, up to 300k P/E cycles, and excellent disturb margins. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T17:24:45Z (GMT). No. of bitstreams: 1 ntu-94-D89921006-1.pdf: 1090424 bytes, checksum: a402c53df16681fbf9c174b9fae91e81 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | 摘要. I
Abstract. III Figure Captions. VII Chapter 1 Introduction. 1 1.1 Non-Volatile Memory Introduction. 1 1.2 An Outline of the Dissertation 2 Chapter 2 The Process and Electrical Characterization of a Split-Gate Cell. 6 2.1 Effect of Erase Voltage on Tunnel Oxide Trapping and Endurance Performance. 6 2.2 Erase Voltage Optimization. 11 Chapter 3 Full-Featured EEPROM Using High Source-Coupling Ratio Design. 20 3.1 Brief Introduction. 20 3.2 Device Fabrication. 21 3.3 Results and Discussion. 21 3.4 Summary. 23 Chapter 4 P-channel Split-Gate Cell with a Field-Enhanced Structure. 33 4.1 Brief Introduction. 33 4.2 Device Fabrication. 34 4.3 Cell Characterization. 34 4.4 Summary. 36 Chapter 5 Using an Ammonia Treatment to Improve the Floating-Gate Spacing. 46 5.1 Brief Introduction. 46 5.2 Experiment. 46 5.3 Results and Discussion. 47 5.4 Summary. 48 Chapter 6 Shrinkable Triple Self-Aligned Field-Enhanced Split-Gate Flash Memory. 55 6.1 Brief Introduction. 55 6.2 Device Fabrication. 55 6.3 Cell Characterization. 57 6.4 Summary. 59 Chapter 7 Summary. 72 7.1 Conclusion. 72 7.2 Prospective Plans. 74 References. 76 | |
dc.language.iso | en | |
dc.title | 分離式閘極非揮發性記憶體之研究 | zh_TW |
dc.title | The Study of Split-Gate Non-Volatile Memory Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-1 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 金雅琴,洪志旺,劉致為,王維新,胡振國,雷添福,鄭晃忠 | |
dc.subject.keyword | 分離式閘極,自我對準,多晶矽尖角,非揮發性記憶體,快閃記憶體, | zh_TW |
dc.subject.keyword | field-enhanced structure,disturb,flash,split-gate,source-coupling,full-feature EEPROM,p-channel,self-aligned, | en |
dc.relation.page | 85 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-01-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-94-1.pdf 目前未授權公開取用 | 1.06 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。