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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38729完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顏嗣鈞 | |
| dc.contributor.author | Kuo-Sheng Wu | en |
| dc.contributor.author | 吳國勝 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:43:45Z | - |
| dc.date.available | 2005-07-21 | |
| dc.date.copyright | 2005-07-21 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-06-30 | |
| dc.identifier.citation | [1] Evangeline F. Y. Young, Chris C. N. Chu and M.L. Ho, “Placement Constraints in Floorplan Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Issue 7, pp. 735-745, 2004
[2] Evangeline F. Y. Young, Chris C. N. Chu and M.L. Ho, “A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design,” Proceedings of ASP-DAC, pp. 661-667, 2002 [3] I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Aziz, A. and D.F. Wong, “Integrated Power Supply Planning and Floorplanning,” Proceedings of the ASP-DAC, pp. 589-594, 2001 [4] Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai and D.F. Wong, “Floorplanning with Power Supply Noise Avoidance,” Proceedings of the ASP-DAC, pp. 427-430, 2003 [5] H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, “VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1518-1524, 1996 [6] H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, “Rectangle Packing Based Module Placement,” IEEE/ACM International Conference on Computer-Aided Design, pp. 472-479, 1995 [7] Hung-Ming Chen, Hai Zhou, F.Y. Young, D.F. Wong, H.H. Yang and N. Sherwani, “Integrated Floorplanning and Interconnect Planning,” IEEE/ACM International Conference on Computer-Aided Design, pp. 354-357, 1999 [8] Kai-Yuan Chao and D.F. Wong, “Floorplanning for Low Power Designs,” IEEE International Symposium on Circuits and Systems, pp. 45-48, 1995 [9] Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, “Robust Fixed-Outline Floorplanning through Evolutionary Search,” Proceedings of the ASP-DAC, pp.42-44, 2004 [10] De-Sheng Chen, Chang-Tzu Lin and Yi-Wen Wang, “Non-Slicing Floorplans with Boundary Constraints using Generalized Polish Expression,” Proceedings of the ASP-DAC, pp.342-345, 2003 [11] Hua Xiang, Xiaoping Tang and D.F. Wong, “Bus-Driven Floorplanning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1522-1530, 2004 [12] F.Y. Young and D.F. Wong, “Slicing Floorplans with Pre-Placed Modules,” IEEE/ACM International Conference on Computer-Aided Design, pp. 252-258, 1998 [13] F.Y. Young, D.F. Wong and H.H. Yang, “Slicing Floorplans with Range Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.272-278, 2000 [14] F.Y. Young, D.F. Wong and H.H. Yang, “Slicing Floorplans with Boundary Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.17-20, 1999 [15] En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai and Ting-Chi Wang, “Slicing Floorplan Design with Boundary-Constrained Modules,” Proceedings of the international symposium on Physical design, pp. 124-129, 2001 [16] Wing Seung Yuen and Fung Yu Young, “Slicing Floorplan with Clustering Constraints,” Proceedings of the ASP-DAC, pp. 503-508, 2001 [17] D. F. Wong and C. L. Liu, “A New Algorithm for Floorplan Design,” Proceedings of the ACM/IEEE conference on Design automation Conference, pp. 101-107, 1986 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38729 | - |
| dc.description.abstract | 超大型積體電路(VLSI)的快速發展，目前已經進展到深次微米(deep sub-micron)的程度。在深次微米的設計中，由於供應電源電壓(supply voltage)的減低，要使電路能夠正常且有效率地運作，維持穩定且充足的電源供應(power supply)成為一個首要需要考慮的議題。在傳統的設計流程中，電源供應規劃一直到最後繞線(routing)的階段才受到考慮；在最後的階段才做規劃，容易導致可變動的空間少、可修改的彈性有限，某些問題也許無法被解決，必須退回前幾個階段重新做設計，浪費時間與人力。
另外，在平面規劃(floorplaning)階段，工程師常會為了某些特殊的需求，而將某些模組區塊擺放於特定的位置，例如：將有資料相關性的區塊擺放成一排或將某些區塊靠邊擺放；這些限制即為擺放限制(placement constraints)，其中包括了：隊列限制(alignment constraint)、毗鄰限制(abutment constraint)、預先放置(pre-place)、範圍限制(range constraint)、邊界限制(boundary constraint)、及叢集限制(clustering)等。我們採用以序列配對(sequence pair)的表示方法，來處理一般的Non-slicing平面規劃問題。 本文主要探討：以擺放限制為基礎，同時考慮電路區塊功率消耗分佈之平均性的平面規劃問題。將電路區塊所需消耗的功率均勻地擺放，以期能減少因為功率需求過於擁擠，而造成供給電源不足(insufficient power supply)或區域性過熱(local hot spot)等問題，影響電路正常的運作。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:43:45Z (GMT). No. of bitstreams: 1 ntu-94-R92921098-1.pdf: 1269311 bytes, checksum: e6f649437f477f1d0147c6998c949a14 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 摘要 4
第一章 序論 5 1.1 平面規劃於超大型積體電路之實體設計 7 1.2 相關研究 10 1.3 問題定義 12 1.3.1 擺放限制 12 1.3.2 功率分佈 14 1.3.3 擺放限制+功率分佈 15 1.4 論文架構 16 第二章 理論基礎 17 2.1 SLICING/NON-SLICING平面規劃 17 2.2 序列配對 (SEQUENCE PAIR) 18 2.3 限制圖形 (CONSTRAINT GRAPHS) 19 2.4序列配對+限制圖形 20 2.5 使用限制圖形處理模組擺放限制 22 2.5.1 隊列限制 (alignment constraint) 22 2.5.2 毗鄰限制 (abutment constraint) 23 2.5.3 預先放置 (pre-place) 24 2.5.4 範圍限制 (range constraint) 25 2.5.5 邊界限制 (boundary constraint) 26 2.5.6 叢集限制 (clustering) 27 2.6 電源幫浦 28 第三章 演算法 29 3.1 BELLMAN-FORD ALGORITHM 30 3.1.1使用Bellman-Ford Algorithm找出各節點座標 31 3.2 SIMULATED ANNEALING ALGORITHM 32 3.2.1 序列配對中的移動方式(Moves) 34 3.2.2 考慮功率分佈 36 3.2.3 Multi-Stage Simulated Annealing 38 3.2.4 新的成本函數 39 3.2.5 標準化成本函數 41 3.3 程式流程圖 42 第四章 實驗結果 43 4.1 APTE 45 4.2 XEROX 46 4.3 HP 47 4.4 AMI33 48 4.4.1 ami33 (divide 4 power regions) 48 4.4.2 ami33 (divide 9 power regions) 50 4.5 AMI49 52 4.5.1 ami49 (divide 4 power regions) 52 4.5.2 ami49 (divide 9 power regions) 54 4.6 綜合比較 56 第五章 結論 58 第六章 參考文獻 59 | |
| dc.language.iso | zh-TW | |
| dc.subject | 平面規劃 | zh_TW |
| dc.subject | floorplanning | en |
| dc.title | 考慮功率分佈及擺放限制之平面規劃設計 | zh_TW |
| dc.title | Power Distribution with Placement Constraints in Floorplanning | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 莊仁輝,呂學一,雷欽隆,黃秋煌 | |
| dc.subject.keyword | 平面規劃, | zh_TW |
| dc.subject.keyword | floorplanning, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-06-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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