雙閘式絕緣體上矽金氧半元件當上閘極為N+/ 下閘極為P+多晶矽時的分析

Abstract

本論文中提出了雙閘全解離絕緣體上矽金氧半元件當上下閘極分別為N+/P+時轉折電壓與汲極電流的分析。 第二章說明一般在閘極對稱情形下，雙閘全解離絕緣體上矽金氧半元件的臨界電壓模型，並考慮不同通道長度的情形。 第三章中討論雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時，轉折電壓的模型，並藉由二維元件模擬軟體(MEDICI)驗證之。 第四章中討論雙閘全解離絕緣體上矽金氧半元件當上下閘極為N+ / P+多晶矽時，汲極電流的模型，並藉由二維元件模擬軟體(MEDICI)驗證之。

This thesis reports an analysis of double-gate SOI CMOS devices using top N+/Bottom P+ poly gate structure. In chapter 2, we discuss the threshold voltage model of the normal DG FD SOI PMOS devices without considering gate misalignment effect in different channel length. In chapter 3,we report an analytical short-channel effect (SCE) transition voltage model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ polysilicon top/bottom gate. The existence of the transition voltage is due to the simultaneous turn-on of the bottom channel in addition to the top channel. As verified by 2D simulation results, this analytical transition voltage model provides a well prediction of the SCE transition voltage behavior of the devices. In chapter 4, we report an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ poly top/bottom gate considering the threshold/transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the 100nm DG FD SOI NMOS device with the n+/p+ poly top/bottom gate as verified by the 2D simulation results.