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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38513完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Yen-Ting Lin | en |
| dc.contributor.author | 林彥廷 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:35:51Z | - |
| dc.date.available | 2005-07-22 | |
| dc.date.copyright | 2005-07-22 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-07 | |
| dc.identifier.citation | [1] D. Kahng and M. M. Atalla, “Silicon Dioxide Filed Surface Devices,” Device Research Conf., Pittsburgh, 1960.
[2] G. E. Moore, “Progress in Digital Integrated Circuit,” IEDM Tech. Dig., p.11, 1975. [3] C. C. Ting, Y. H. Shih, and J. G. Hwu, “Ultra low Leakage Characteristics of Ultra thin Gate Oxides (3nm) Prepared by Anodization Followed by High-temperature Annealing,” IEEE Trans. Electron Devices, vol.49, no.1, pp.179, 2002. [4] C. H Choi, Y. Wu, J. S. Goo, Z. Yu, and R. W. Dutton, “ Capacitance Reconstruction from Measured C-V in High Leakage, Nitride/Oxide, MOS,” IEEE Trans. Electron Devices, vol.47, pp.1843, 2000. [5] K. J. Yang, C. Hu, “MOS Capacitance Measurements for High-leakage Thin Dielectrics,” ” IEEE Trans. on Electron Device, vol.46, no.7, p.1500, 1999. [6] K. J. Yang, Y. C. King, C. Hu, “Quantum Effect in Oxide thickness Determination from Capacitance measurement,” Tech. Digest VLSI Symp, p.77, 1999. [7] R. Rios et al, Tech. Dig. Int. Electron Devices Meet. , pp.937, 1995. [8] Berkeley Device Group. [Online]. Available: www.device.eecs.berkeley.edu /qmcv/html. [9] G. Eftekhari, “Effects of Oxide Thickness and Oxidation Parameters on the Electrical Characteristics of Thin Oxides Grown by Rapid Thermal Oxidation of Si in N2O,” Journal of the Electrochemical Society, vol.141, no.11, Nov, p.3222-3225, 1994. [10] W. S. Lu, K. C. Lin, J. G. Hwu, “Process Dependency of Radiation Hardness of Rapid Thermal Reoxidized Nitrided Gate Oxides,” IEEE Transactions on Electron Devices, vol.40, no.9, Sep, p.1597-1602, 1993. [11] G. W. Yoon, A. B. Joshi, J. Kim, G. Q. Lo, D. L. Kwong, “Effects of Growth Temperature on TDDB Characteristics of N2O-Grown Oxides,” IEEE Electron Device Letters, vol.13, no.12, Dec, p.606-608, 1992. [12] J. Ahn, D. L. Kwong, ”Electrical Properties of MOSFET's with N2O-Nitrided LPCVD SiO2 Gate Dielectrics,” IEEE Electron Device Letters, vol.13, no.9, Sep, p.494-496, 1992. [13] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” Journal of the Electrochemical Society, vol.104, p.230, 1957. [14] P. F. Schmidt, T. W. O’Keeffe, J. Oroshnik, and A. E. Owen, “Doped Anodic Oxide Films for Device Fabrication in Silicon: Diffusion Sources of Controlled Composition, and Diffusion Results,” Journal of the Electrochemical Society, vol. 112, no. 8, p.800-807, 1965. [15] G. C. Jain, A. Prasad and B. C. Chakravarty, “On the Mechanism of the Anodic Oxidation of Si at Constant Voltage,” Journal of the Electrochemical Society, vol.126, no.1, p.89-92, 1979. [16] S. K. Sharma, B. C. Chakravarty, S. N. Singh, B. K. Das, D. C. Parashar, J. Rai and P. K. Gupta, “Kinetics of Growth of Thin Anodic Oxides of silicon at Constant Voltages,” Journal of Physics and Chemistry of Solids, vol.50, no.7, p. 679-684, 1989. [17] J. A. Bardwell, N. Draper, and P. Schmuki, “Growth and Characterization of Anodic Oxides on Si(100) Formed in 0.1 M Hydrochloric Acid,” Journal of Applied Physics, vol.79, no.11, p.8761-8769, 1996. [18] Vitali Parkhutik, “New Effects in the Kinetics of the Electrochemical Oxidation of Silicon,” Electrochimica Acta, vol.45, p.3249-3254, 2000. [19] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation,” Journal of Molecular Structure, p. 607-610, 1999. [20] Sorab K. Ghandhi, VLSI Fabrication Principles, 2nd ed., Wiley-Interscience, p. 487-495, 1994. [21] H. J. Lewerenz, “Anodic Oxides on Silicon,” Electrochimica Acta, vol.37, no.5, p.847-864, 1992. [22] B. Brar, G. D. Wilk, and A. C. Seabaugh, “Direct Extraction of the Electron Tunneling Effective Mass in Ultrathin SiO2,” Applied Physics Letter, vol.69, p.2728, 1996. [23] A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967. [24] M. Y. Doghish, and F. D. Ho, “A Comprehensive Analytical Model for Metal Insulator Semiconductor (MIS) Devices,” IEEE Transactions on Electron Devices, vol.39, p.2771, 1992. [25] Y. P. Lin, J. G. Hwu, “Suboxide Characteristics in Ultrathin Oxides Grown Under Novel Oxidation Processes,” Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films, vol.22, no.6, p.2265, 2004. [26] T. P. Lin, J. K. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” Journal of the Electrochemical Society, vol.151, no.12, p.G853, 2004. [27] S. T. Pantelides, S. N. Rashkeev, R. Buczko, D. M. Fleetwood, R. D. Schrimpf, “Reactions of Hydrogen with Si-SiO2 Interfaces,” IEEE Transactions on Nuclear Science, vol.47, no.6 III, p.2262, 2000. [28] S. N. Rashkeev, D. M. Fleetwood, R. D. Schrimpf, S. T. Pantelides, “Defect Generation by Hydrogen at the Si-SiO2 Interface,” Physical Review Letters, vol.87, no.16, p.165506/1, 2001. [29] C. S. Kuo, F. J. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, J. G. Hwu, “High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film in Nitric Acid Followed by High-Temperature Annealing,” IEEE Transactions on Electron Devices, vol.51, no.6, p.854, 2004. [30] K. Sekine, S. Inumiya, M. Sato, A. Kaneko, K. Eguchi, Y. Tsunashima, “Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current,” IEDM, 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38513 | - |
| dc.description.abstract | 近年來由於積體電路元件尺寸不斷縮小，對閘極氧化層的要求也越嚴格，對於超薄閘極氧化層的研究，當縮小氧化層厚度的同時也能降低漏電流並提高穩定度方面議題也相形重要。本篇論文乃提出室溫陽極氧化備製來補償快速熱製程氧化層的缺陷，利用此方法所長出來的氧化層將會有較小的漏電流。我們先介紹直流陽極氧化的成長機制，接著以交直流的技術以補償超薄閘極氧化層，由實驗結果可看出這種技術能改善氧化層的特性。
論文首先簡述對閘極氧化層的研究及整篇論文的動機。在第一章中，對實驗的設備及所使用的量測儀器做簡單的介紹。第二章首先回顧過去對定電壓陽極氧化機制的基本理論，這些模型提出在陽極氧化過程中可能發生的電化學反應。此外，本章利用不同交直流氧化條件來補償快速熱製程氧化層的不完全。探討的效應包括：1. 交流切換頻率。2. 補償時間長短。3. 直流振幅大小。 接著，在第三章我們對無陽極氧化與經過陽極氧化補償後的氧化層做比較，比較在反轉區與聚積區的電流密度，發現在陽極氧化補償後反轉區雖有比較小的漏電流，但隨著時間經過，電流降低速度比較慢。我們所製備氧化層在聚積區的漏電流，與世界標準非常接近，也肯定了交直流陽極氧化補償技術的功效。 | zh_TW |
| dc.description.abstract | The scale of the VLSI device has downsized in recent years. The studies of the ultra-thin gate oxide have progressed rapidly due to strict requirement of the gate dielectric. When gate oxide becomes thinner, it is important to lower the leakage current and improve the reliability. This work proposes room temperature anodic oxidation or anodization (ANO) to compensate the defects existed in the oxides grown by rapid thermal oxidation (RTO). By this method, we can get oxide with lower leakage current and better performance. First, we introduce the mechanism of the direct current ANO. Then, compensate the ultra-thin gate oxide with direct-current superimposed with alternating-current anodization (DAC-ANO) technique. We can find the quality of the oxide has been improved.
In the beginning of this work, we introduce study of the gate oxide and the motivation of this thesis. In chapter 1, the experimental setup and the measurement system are also briefly described. In chapter 2, basic theories about the mechanism of the constant voltage ANO of silicon are reviewed. These models suggest possible electrochemical reactions during the ANO. Besides, we utilize different DAC-ANO conditions to compensate the defects in RTO oxides. The conditions including 1. frequency effect, 2. duration effect, and 3. DC amplitude effect are inspected. Next, in chapter 3, we compare the current densities in inversion region and accumulation region of the RTO oxides with and without ANO-DAC. We found that the leakage current in inversion region is smaller with ANO-DAC compensated, but the current density lowering is slower with time past. We also can get similar current scale with the world level in accumulation region. It confirms the contribution of DAC-ANO. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:35:51Z (GMT). No. of bitstreams: 1 ntu-94-R92943051-1.pdf: 1058826 bytes, checksum: ac03201da8440b48acd6022f47962270 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Chapter 1 Introduction ...................................1
1.1 Motivation....................................1 1.2 The Experimental System and Measurement Tools.2 1.3 Determination of the Ultra-Thin Gate Oxide Thickness by Quantum Mechanical Fitting ......3 Chapter 2 RTO Compensated With Direct-Current Superimposed With Alternating-Current Anodization (DAC-ANO) Technique......................................11 2.1 Introduction ................................11 2.1.1 Growth Model for Constant-Voltage Anodization of Silicon....................12 2.1.2 Direct-Current Superimposed With Alternating- Current Anodization of Silicon...................................14 2.2 Experimental Design and Device Fabrication...15 2.3 RTO Followed by DAC-ANO Compensation.........16 2.3.1 Analytical Model for Tunneling in MOS Diode.....................................16 2.3.2 Frequency Effect in DAC-ANO...............18 2.3.3 Duration Effect in DAC-ANO................19 2.3.4 DC Amplitude Effect in DAC-ANO............21 2.4 Summary......................................23 Chapter 3 Comparison of The Electrical Characteristics between RTO and RTO-DAC-ANO Oxides.............40 3.1 Introduction.................................40 3.2 Observation in I-V Characteristics...........41 3.2.1 I-V in Inversion Region...................41 3.2.2 I-V in Saturation Region..................43 3.3 Oxides Growth in Long Term Duration..........43 3.4 Summary......................................44 Chapter 4 Conclusion ....................................55 References ..............................................57 | |
| dc.language.iso | en | |
| dc.subject | 陽極氧化 | zh_TW |
| dc.subject | 二氧化矽 | zh_TW |
| dc.subject | 氧化層 | zh_TW |
| dc.subject | oxide | en |
| dc.subject | anodization | en |
| dc.title | 利用交直流陽極氧化補償技術改善超薄閘極氧化層品質 | zh_TW |
| dc.title | Quality Improvement in Ultra-Thin Gate Oxides by Direct-Current Superimposed With Alternating-Current Anodization (DAC-ANO) Compensation Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪志旺(J. W. Hong),鄭晃忠(Huang-Chung Cheng) | |
| dc.subject.keyword | 陽極氧化,氧化層,二氧化矽, | zh_TW |
| dc.subject.keyword | oxide,anodization, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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