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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 裝東漢 | |
dc.contributor.author | Wei-Hung Lin | en |
dc.contributor.author | 林威宏 | zh_TW |
dc.date.accessioned | 2021-06-13T16:29:22Z | - |
dc.date.available | 2005-07-19 | |
dc.date.copyright | 2005-07-19 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-13 | |
dc.identifier.citation | 1. J. H. Lau, “Ball Grid Array Technology”, by McGraw-Hill, 1995.
2. C. A. Harper, Electronic Packaging and Interconnection Handbook, McGraw-Hill, 2000. 3. R. R. Tummala, Fundamental of Microsystems Packaging, McGraw-Hill, 2001. 4. R. R. Tummala, “Industry/Academia Collaboration in EMS: The Academic Perspective”, Georgia Institute of Technology, 2001, pp.1-23. 5. L. Nguyen, “CSP Level Packaging”, IEEE CPMT Meeting, 2002, pp1-28. 6. C. S. Chang, A. Oscilowski, and R. C. Bracken, ”Future Challenges in Electronics Packaging”, Circuits & Devices, 1998, pp.45-54. 7. S.H. Fan, Y.C. Chan, C.W. Tang, JKL Lai, “Aging studies of PBGA solder joints reflowed at different conveyor speeds “, Transactions on Advanced Packaging, Vol. 24, 2001, pp.46-492. 8. J. H. Okura, S. Shetty, B. Ramakrishnan, A. Dasgupta, J. F. J. M. Caers, “Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies”, Microelectronics Reliability, Vol. 40, 2000, pp.1173-1180. 9. Lau, S. W. Ricky Lee, “Fracture Mechanics Analysis of Low Cost Solder Bumped Flip Chip Assemblies With Imperfect Underfills”, Transactions of the ASME, Vol. 122, 2000, pp.306-310. 10. R. Haug , U. Behner,C. P. Czaya, H. Q. Jiang, S. Kotthaus, R. Schuetz, C. P. O. Treutler, “Low-cost direct chip attach: Comparison of SMD compatible FC soldering with anisotropically conductive adhesive FC bonding”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 23, 2000, pp.12-18. 11. J. P. Langan, “Advantages of Electroless Ni Au on SMT Boards”, Vol. 79, 1992, pp.44-45. 12. Goldmann, L. S., P. A. Totta, “Chip Level Interconnect: Solder Bunded Flip Chip”, in Chip on Board Technologies for Multichip Modules, Lau, J. H., ed., Van Nostrand Reinhold, New York, 1994, pp.228-250. 13. T. Ritzdorf and B. Batz, “Fountain Electroplating of Lead Tin Solder for Semiconductor Flip Chip Applications”, Proceedings of the AESF Annual Technical Conference, pp.257-262, 1996. 14. P. Annala, J. Kaitila, and J. Salonen, “Electroplated Solder Alloys for Flip Chip Interconnections”, Physica Scripta, Vol. T69, pp.115-118, 1997. 15. S. Watanabe, Y. Ibara, Y. Kitahara, T. Kobayashi, and S. Wakabayashi, “Solder bump fabrication on wafers by electroplating process”, Proceedings of the IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, pp.110-115, 1997. 16. Y. Nakamura, et al., “Advanced LSI Package Using Stud-Bump-Bonding Technology”, International conference on Multichip Modules, pp.302-307, 1995. 17. S. Zama, et al., “Flip Chip Interconnect Systems Using Copper Wire Stud Bump and Lead Free Solder”, IEEE Transactions on Electronics Packaging Manufacturing, Vol. 24, No. 4, pp.261-268, 2001. 18. M. Klein, H. Oppermann, R. Kalicki, R. Aschenbrenner, H. Reichl, “Single chip bumping and reliability for flip chip processes”, Microelectronics Reliability, Vol. 39, 1999, pp.1389-1397. 19. Hirokazu Ezawa, Masahiro Miyata, Soichi Honma, “Eutectic Sn-Ag Solder Bump Process for ULSI Flip Chip Technology”, Electronic Components and Technology Conference, 2000, pp.1095-1100. 20. S. Y. Jang, J. Wolf, O. Ehrmann, H. Reichl, K. W. Paik, “Pb-free Sn-3.5Ag wafer-bumping process and UBM(under bump metallurgy) study”, Microsystem Technologies, Vol. 7, 2002, pp.269-272. 21. T. Kondo, K. Obata, T. Takeuchi, S. Masaki, “Bright Tin-Silver Alloy Electrodeposition from an Organic Sulfonate Bath Containing Pyrophosphae, Iodide and Triethanolamine as Chelating Agents”, Plating and Surface Finishing, Feb, 1998, pp.51-55. 22. Wu CML, Chau ML, “Degradation of flip-chip-on-glass interconnection with ACF under high humidity and thermal aging”, Soldering and Surface Mount Technology, Vol. 14, 2002 , pp.51-58. 23. Frank Stepniak, “Conversion of the under bump metallurgy into intermetallics: the impact on flip chip reliability”, Microelectronics Reliability, Vol. 41, 2001, pp.735-744 24. C. Ernhart and S. Scarr, presented at the ACYF research conference, New Directions in Child and Family Research, 1991. 25. W.J. Plumbridge, Journal of Materials Science, Vol 31, 1996, p2501-2514 26. J. Glazer, ”International Materials Reciews”, Vol 40, 1995, p65-93. 27. Draft proposal for a European Parliament and Council Directive on Waste Electronic Equipment, June 2000. 28. ”Eco-Technology 2000”, Japanese Printed Circuit Association Show 2000, Japan 29. “Lead-Free Project Focuses on Electronics Assemblies”, Advanced Packaging, February 2000. 30. K.N. Tu, “Cu/Sn Interface Reactions: thin-film case versus bulk case”, Materials Chemistry and Physics, 46, 1996, p.217-223. 31. N.C Lee,”『1998先進電子封裝技術趨勢研討會』講義”, 1998, p8/1-8/8 32. T.B. Massalski, Binary Alloy Phase Diagrams, 2nd ed, p.3417. 33. D. Brandon and W.D. Kaplan, “Joining Processes: an Introduction”, John Wiley and Sons Ltd,1997. 34. E.P. Wood and K.L. Nimmo, “In Search of New Lead-free Electronic Solders”, Journal of Electronic Materials, Vol. 23,1994, p.709-713. 35. H.M. Lee, S.W. Yoon and B.J. Lee, ”Thermodynamic Predictionof Interface Phase at Cu/Solder Joints”, Journal of Electronic Materials, Vol 27, No 11, 1998, p.1161-1166. 36. K. Suganuma, T. Murata, H. Noguchi, and Y. Toyoda, “Heat resistance of Sn-9Zn solder/Cu interface with or without coating”, Journal of Material Research, 15(4), Apr 2000, pp.884-891. 37. N.C. Lee, “Lead-Free Soldering-Where The World Is Going” 38. Paul Harris,” Interfacial reactions of tin-zinc-bismuth alloys”, Soldering & Surface Mount Technology, 1999, p46-52. 39. T. Sugizaki, H. Nakao, T. Kimura, and T. Watanabe, “BGA jointing property of Sn-8.8mass%Zn and Sn-8.0Zmass%Zn-3.0mass%Bi solder on electroless nickel-phosphorus/immersion gold plated substrates”, Materials Transactions, 44(9), Sep 2003, pp.1790-1796. 40. S.W. Yoon, J.R. Son, H.M. Lee and B.J. Lee, “Thermodynamics – Aided-Alloy Design and Evaluation of Pb-free Solder, Sn-Bi-In-Zn System”, Acta Mater., Vol. 45, No 3, 1997, pp.951-960. 41. S.W. Yoon, W.K. Choi and H.M. Lee, “Interfacial Reaction between Sn-1Bi-5In-9Zn Solder and Cu Substrate”, Scripta Materialia,1999, Vol 40, No 3, p327-332. 42. K.L. Lin, and C.L. Shih, “Wetting interaction between Sn-Zn-Ag solders and Cu”, Journal of Electronic Materials, 32(2), Feb 2003, pp.95-100. 43. C.M. Chuang, H.T. Hung, P.C. Liu, and K.L. Lin, “The interfacial reaction between Sn-Zn-Ag-Ga-Al solders and metallized Cu substrates”, Journal of Electronic Materials, 33(1), Jan 2004, pp.7-13. 44. K.L. Lin, K.I. Chen, and P.C. Shi, “A potential drop-in replacement for eutectic Sn-Pb solder-the Sn-Zn-Ag-Al-Ga solder”, Journal of Electronic Materials, 32(12), Dec 2003, pp.1490-1495. 45. K.I. Chen, and K.L. Lin, “The microstructures and mechanical properties of the Sn-Zn-Ag-Al-Ga solder alloys – the effect of Ga”, Journal of Electronic Materials, 32(10), Oct 2003, pp.1111-1116. 46. R.K. Shiue, L.W. Tsay, C.L. Lin, and J.L. Ou, “The reliability study of selected Sn-Zn based lead-free solders on Au/Ni-P/Cu substrate” Microelectronics Reliability, 43(3), Mar 2003, pp.453-463. 47. C.M.L. Wu, C.M.T. Law, D.Q. Yu, and L. Wang, “The wettability and microstructure of Sn-Zn-RE alloys”, Journal of Electronic Materials, 32(2), Feb 2003, pp.63-69. 48. C.M.L. Wu, D.Q. Yu, C.M.T. Law, and L. Wang, “The properties of Sn-9Zn lead-free solder alloys doped with trace rare earth elements”, Journal of Electronic Materials, 31(9), Sep 2002, pp.921-927. 49. Tia-Marje Korhonen, V. Vuorinen, and J.K. Kivilahti, “Interconnections Based on Bi-Coated SnAg Solder Balls”, IEEE Transactions on Advanced Packaging, 24(4), Nov 2001, pp.515-520. 50. Mordechay Schlesinger, Milan Paunovic, “Modern Electroplating”, John Wiley and Sons Inc, New York, 2000. 51. Manfred Jordan, “The Electrodeposition of Tin and its Alloys”, Galvanotechnik-Leiterplattentechnik, Germany, 1995. 52. St. Vitkova, V. Ivanova, G. Raichevsky, “Electodeposition of low tin content zinc-tin alloys”, Surface and Coatings Technology, Vol. 82, 1996, pp.226-231. 53. O. A. Ashiru, J. Shirokoff, “Electrodeposition and characterization of tin-zinc alloy coatings”, Appied Surface Science, Vol. 103, 1996, pp. 159-169. 54. G.L. Baldini, A. Scorzoni, and F. Tamarrif, “Resistance decay after electromigration as the effect of mechanical-stress relaxation”, Microelectronics and Reliability, 33(11-12), Sep 1993, pp.1841-1844. 55. E. Castano, and J. Maiz, “Physical analysis of electromigration damage under non-DC conditions”, Microelectronics and Reliabilty, 33(8), Jun 1993, pp.1189-1198. 56. J.J Clement, “Vacancy supersaturation model for electromigration failure under DC and pulsed DC stress”, Journal of Applied Physics, 71(9), May 1992, pp.4264-4268. 57. H. Kawasaki, C. Lee, and T.K. Yu, “Realistic electromigration lifetime projection of VLSI interconnects”, Thin Solid Films, 253(1-2), Dec 1994, pp.508-512. 58. D.W. Malone, and R.E. Hummel, “Electromigration in integrated circuits”, Critical Reviews in Solid State and Materials Sciences, 22(3), 1997, pp.199-238. 59. H. Ishida, “Microscopic theory of the wind force for adsorbates on simple metal-surfaces”, Physical Review B, 49(20), May 1994, pp.14610-14618. 60. J.P. Dekker, A. Lodder, and J. Vanek, “Theory for the electromigration wind force in dilute alloys”, Physical Review B, 56(19), Nov 1997, pp.12167-12177. 61. P.J. Rous, “Electromigration wind force at stepped Al surfaces”, Physical Review B, 59(11), Mar 1999, pp.7719-7723. 62. D.N. Bly, and P.J. Rous, “Theoretical study of the electromigration wind force for adatom migration at metal surfaces”, Physical Review B, 53(20), May 1996, pp.13909-13920. 63. C.Y. Chang, and S.M. Sze, “ULSI Technology”, the McGraw-Hill, 1996, pp.663. 64. 吳文發and秦玉龍,『電遷移效應對銅導線可靠度之影響』,奈米通訊-第六卷第一期。 65. D.B. Knorr, D.P. Tracy, and K.P. Prdbell, “Correlation of texture with electromigration behavior in Al metallization”, Applied Physics Letters, 59(25), Dec 1991, pp.3241-3243. 66. J.A. Nucci, R.R. Keller, J.E. Sanchez, and Y. ShachamDiamand, “Local crystallographic texture and voiding in passivated copper interconnects”, Applied Physics Latters, 69(26), Dec 1996, pp.4017-4019. 67. D.P. Field, J.E. Sanchez, P.R. Besser, and D.J. Dingley, “Analysis of grain-boundary structure in Al-Cu interconnects”, Journal of Applied Physics, 82(5), Sep 1997, pp.2383-2392. 68. A. Gladkikh, M. Karpovski, A. Palevski, and Y.S. Kaganovskii, “Effect of microstructure on electromigration kinetics in Cu lines”, Journal of Physics-Applied Physics, 31(14), Jul 1998, pp.1626-1629. 69. Y. Ji, T.X. Zhong, Z.G. Li, X.D. Wang, D. Luo, Y. Xia, and Z.M. Liu, “Grain structure and crystallographic orientation in Cu damascene lines”, Microelectronic Engineering, 71(2), Feb 2004, 182-189. 70. D.H. Kim, “Electromigration”, http://SemiTechnik.com 71. Aris Christou, “Electromigration and Electronic Device Degradation”, John Wiley & Sons, Inc., 1994. 72. A.J. Walker, K.Y. Le, J. Shearer, and M. Mahajani, “Analysis of tungsten and titanium migration during ESD contact burnout”, IEEE Transactions on Electron Devices, 50(7), Jul 2003, pp.1617-1622. 73. A. Gungor, K. Bamak, A.D. Rollett, C. Cabral, and J.M.E. Harper, “Texture and resistivity of dilute binary Cu(Al), Cu(In), Cu(Ti), Cu(Nb), Cu(Ir), and Cu(W) alloy thin films”, Journal of Vacuum Science & Technology B, 20(6), Nov-Dec 2002, pp.2314-2319. 74. M. Paniccia, P. Flinn, and R. reifenberger, “Scanning Probe Microscopy studies of Electromigration in Electroplated Au wires”, Journal of Applied Physics, 73(12), Jun 1993, pp.8189-8197. 75. H. You, R.P. Chiarello, H.K. Kim, and K.G. Vandervoort, “X-ray reflectivity and scanning-tunneling-microscope study of kinetic roughening of sputter-deposited Gold-films during growth”, Physical Review Letters, 70(19), May 1993, pp.2900-2903. 76. M. Aguilar, A.I. Oliva, P. Quintana, and J.L. Pena, “Electromigration in gold thin films”, Thin Solid Films, 317(1-2), Apr 1998, pp.189-192. 77. A. Panin, A. Shugurov, and J. Schreiber, “Fractal analysis of electromigration-induced changes of surface topography in Au conductor lines”, Surface Science, 524(1-3), Feb 2003, pp.191-198. 78. C.K. Hu, R. Rosenberg, and K.Y. Lee, “Electromigration path in Cu thin-film lines”, Applied Physics Letters, 74(20), May 1999, pp.2945-2947. 79. S.P. Hau-Riege, and C.V. Thompson, “The effects of the mechanical properties of the confinement material on electromigration in metallic interconnects”, Journal of Materials Research, 15(8), Aug 2000, pp.1797-1802. 80. S.P. Hau-Riege, and C.V. Thompson, “Electromigration in Cu interconnects with very different grain structures”, Applied Physics Letters, 78(22), May 2001, pp.3451-3453. 81. C.K. Hu, L. Gignac, R. Rosenberg, E. Liniger, J. Rubino, C. Sambucetti, A. Domenicucci, X. Chen, and A.K. Stamper, “Reduced electromigration of Cu wires by surface coating”, Applied Physics Letters, 81(10), Sep 2002, pp.1782-1784. 82. C.S. Hau-Riege, “An introduction to cu electromigration”, Microelectronics Reliability, 44(2), Feb 2004, pp.195-205. 83. E. Kolawa, J.S. Chen, J.S. Reid, P.J. Pokela, and M.A. Nicolet, “Tantalum-based diffusion-barriers in Si/Cu VLSI metallizations”, Journal of Applied Physics, 70(3), Aug 1991, pp.1369-1373. 84. H. Ono, T. Nakano, and T. Ohta, “Diffusion Barrier effects of transition-metals for Cu/M/Si Multilayers(M=Cr, Ti, Nb, Mo, Ta, W)”, Applied Physics Letters, 64(12), Mar 1994, pp.1511-1513. 85. J.H. Zhao, “Electromigration and Electronic Device Degradation, Wiley, 1994, pp.171. 86. A. Buerke, H. Wendrock, K. Wetzig, “Study of Electromigration Damage in Al Interconnect Lines inside a SEM”, Crystal Research Technology, 35(6-7), 2000, pp.721-730. 87. H. Wang and C. Bruynseraede, “Impact of current crowding on electromigration- induced mass transport”, Applied Physics Letters, 84(4), Jan 2004, pp.517-519. 88. C.Y. Liu, C. Chen, C.N. Liao, and K.N. Tu, “Microstructure-electromigration correlation in a thin stripe of eutectic SnPb solder stressed between Cu electrodes”, Applied Physics Letters, Vol. 75(1), 1999, pp. 58-60. 89. Q.T. Huynh, C.Y. Liu, Chih Chen, and K.N. Tu, “Electromigration in eutectic SnPb solder lines”, Journal of Applied Physics, Vol. 89(8), 2001, pp. 4332-4335. 90. H.B. Huntingtion, in Diffusion in Solids: Recent Development, edited by A.S. Nowick and J.J. Burtion (Academic, New York, 1974), pp. 303. 91. S. Brandenbery and S. Yeh, in Surface Mount International Conference and Exposition, SMI 98 Proceedings (1998), pp. 337. 92. T.Y. Lee and K.N. Tu, “Electromigration of eutectic SnPb and SnAg3.8Cu0.7 flip chip solder bumps and under-bump metallization”, Journal of Applied Physics, Vol. 90(9), 2001, pp. 4502-4508. 93. T.Y. Lee and K.N. Tu, S.M. Kuo, and D.R. Frear, “Electromigration of eutectic SnPb solder interconnects for flip chip technology”, Journal of Applied Physics, Vol. 89(6), 2001, pp. 3189-3194. 94. C.C. Yeh, W.J. Choi, and K.N. Tu, “Current-crowding-induced electromigration failure in flip chip solder joints”, Applied Physics Letters, Vol. 80(4), 2002, pp. 580-582. 95. H. Ye, C. Basaran, and D. Hopkins, “Thermomigraiton in Pb-Sn solder joints under joule heating during electric current stressing”, Applied Physics Letters, Vol. 82(7), 2003, pp. 1045-1047. 96. H. Ye, C. Basaran, and D.C. Hoplins, “Damage mechanics of microelectronics solder joints under high current densities”, International Journal of Solids and Structures, Vol. 40, 2003, pp. 4021-4032. 97. C.H. Chen and S.W. Chen, “Electromigration effects upon the low-temperature Sn/Ni interfacial reactions”, Materials Research Society, Vol. 18(6), 2003, pp. 1293-1296. 98. C.C. Lu, S.J. Wang, and C.Y. Liu, “Electromigration studies on Sn(Cu) alloy lines”, Journal of Electronic Materials, 32(12), Dec 2003, pp.1515-1522. 99. T.L. Shao, K.C. Lin, and C. Chen, “Electromigration Studies of Flip Chip Sn95-Sb5 Solder Bumps on Cr/Cr-Cu/Cu Under-Bump Metallization”, Journal of Electronic Materials, 32(11), Jun 2003, pp.1278-1283. 100. J. Proost, K. Maex, and L. Delaey, “Electromigration-induced drift in damascene and plasma-etched Al(Cu).Ⅱ. Mass transport mechanisms in bamboo interconnects”, Journal of Applied Physics, 87(1), Jan 2000, pp.99-109. 101. J. Proost, T. Hirato, T. Furuhara, K. Maex, and J.P. Celis, “Microtexture and electromigration-induced drift in electroplated damascene Cu”, Journal of Applied Physics, 87(6), Mar 2000, pp.2792-2802. 102. J.A. Sethian, and J. Wilkening, “A numerical model of stress driven grain boundary diffusion”, Journal of Computational Physics, 193(1), Jan 2004, pp.275-305. 103. A.F. Bower, D. Craft, “Analysis of failure mechanisms in the interconnect lines of microelectronic circuits”, Fatigue & Fracture of Engineering Materials & Structures, 21(5), May 1998, pp.611-630. 104. K.N. Tu, “Recent advances on electromigration in very-large-scale-integration of interconnects”, Journal of Applied Physics, 94(9), Nov 2003, pp.5451-5473. 105. I.A. Blech, “Electromigration in thin aluminum films on titanium nitride”, Journal of Applied Physics, 47(4), April 1976, pp. 1203-1208. 106. I.A. Blech and Conyers Herring, “Stress generation by electromigration”, Applied Physics Letters, 29(3), August 1976, pp. 131-133. 107. I. Shohji and T. Yoshida, “Comparison of low-melting lead-free solders in tensile properties with Sn-Pb eutectic solder”, Journal of materials science: material in electronics, Vol. 15, 2004, pp. 219-223. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38278 | - |
dc.description.abstract | 本實驗中,以電鍍方式製程生長Sn-8Zn-3Bi覆晶銲錫凸塊。 銲錫凸塊以兩階段式之電鍍方式,先鍍上共晶錫鋅再鍍上鉍之方法,其表面之鉍層可防止鋅的氧化。迴銲後,鉍會熔入錫鋅中形成三元的合金。此方式可以克服電鍍液中,一次共鍍三元合金之困難技術。
電遷移之實驗,研究Sn-8Zn-3Bi覆晶銲錫接點在120 oC及150oC下不同之電流密度之條件。其結果,在負極端及正極端界面上,分別生成孔洞和凸起物。此外,在負極端之介金屬化合物會因為電遷移之影響,而轉變成富錫相。且由於極化之現象,在正極端之介金屬化合物的厚度會大於負極端之介金屬化合物。 試片在120 oC及4.5 x 104 A/cm2之平均電流密度下,試片在117小時後失效,且在負極端上可發現清晰之孔洞存在。 同時,此試片在邊界處有融熔之銲錫球存在。 利用電流密度之模擬分析實驗,發現在覆晶接點中,其電流密度並非均勻分佈且有電流叢聚之現象。 這樣的分析結果指出,電流密度之叢聚現象,將會升高電流密度,並造成嚴重的熱焦耳效應和電遷移破壞的發生。 | zh_TW |
dc.description.abstract | In flip chip packaging technology, using electroplating to develop the flip chip solder bumps of Sn-8Zn-3Bi in this study. Investigating two-steps electroplating method, to plate the eutectic Sn-Zn and Bi in order. The Bi layer could cover the surface of Sn-Zn alloy and avoid the oxidation of the Zn. After the reflow, Bi will melt and dissolve into the eutectic Sn-Zn, and then formed the ternary alloy. This method could overcome the difficulty of the co-plating the ternary alloy at a time.
Electromigration of Sn-8Zn-3Bi flip chip solder bumps on Cu has been studied at 120 oC and 150 oC with different current density. Formation of voids and hillocks at the cathode and anode, respectively, has been observed. In addition, a Sn-rich phase has replaced some part of the intermetallic compound of Cu-Zn (γ) which formed between the solder and the Cu pad in the anode side. Due to the polarity effect, the thickness of the intermetallic compound at the anode is thicker than at the cathode. The solder joint fails after 117hrs under 120 oC with an average current density 4.5 x 104 A/cm2 and voids formation at the cathode can clearly be seen after polishing. It is the melting at the edge of the bump that fails the solder. The simulation of the current density distribution indicates that the current density is not uniformly distributed and the current crowding occurs inside the bump. The results indicate that the increase of current density associated with joule heating has affected and enhanced the damage in the solder joint under electromigration. | en |
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dc.description.tableofcontents | 目 錄
中文摘要………………………………………………………………..Ⅰ 英文摘要……………………………………………,…………………..II 目錄…………………………………………………………………….. IV 圖目錄………………………………………………………..…………VI 表目錄…………………………………………………………………..XII 一 前言………………………………………………….…………………………….1 二 理論與文獻回顧…………………………………………………………………..4 2-1電子構裝技術……………………………………………………………….....4 2-2覆晶製程技術及應用………………………………………………………...4 2-3 無鉛銲錫的發展…………………………………………………….….9 2-3-1 Sn-Zn銲錫………………………………………….……………….…..10 2-3-2 Sn-Zn-Bi銲錫及其它銲錫…………………………………………..11 2-4電鍍之原理及應用…………………………..………………………...14 2-5電子構裝之可靠度分析…………………………………………...….16 2-6 電遷移之原理與文獻…………………………………………….…..18 2-6-1電遷移在銲錫之研究………………………………………….....22 2-6-2質遷理論之計算.........................................................…...26 三 實驗方法…………………………………………...…………………………….44 3-1 電鍍無鉛銲錫Sn-Zn………………………………………………………44 3-1-1實驗步驟……………………………………….………………………..44 3-1-2 電鍍錫鋅合金…………………………………………………….…...44 3-2 電鍍覆晶凸塊之實驗方法……………….…………………………..45 3-2-1實驗步驟…………………………………………………………..45 3-2-2實驗方法…………………………………………………………..45 3-3覆晶凸塊之電遷移實驗步驟及方法…………………………………51 四 結果與討論……………………………………………….…….………………..60 4-1 電鍍之研究……………………………………………………………….60 4-1-1電鍍無鉛銲錫Sn-Zn合金………………………………………….60 4-1-2電鍍錫鋅覆晶凸塊之實驗研究……………………………………66 4-1-3電鍍錫鋅鉍覆晶凸塊之實驗研究………………………………………..67 4-2電遷移效應影響之研究……………………………………………………78 4-2-1電流密度為4×103A/cm2及120℃環境下之研究……………..78 4-2-2電流密度為4.5×104A/cm2及120℃環境下之研究…………..85 4-2-3電流密度為1.0×104A/cm2在120℃和150℃環境下之研究.110 4-3電遷移造成破壞之現象……………………………………………...116 4-4電遷移之背向應力……………………………………………………….121 五 結論……………………………………………………………………………..122 六 參考文獻………………………………………………………………………..124 圖 目 錄 圖2.1 不同接合技術示意圖……………………………………......................32 圖2.2為覆晶接合技術示意圖…………………………………………….32 圖2.3 打線接合、自動捲帶接合及覆晶接合之I/O數比較…………33 圖2.4 銲錫凸塊的結構示意圖…………………………………………..33 圖2.5蒸鍍技術配合金屬罩應用銲錫凸塊製作示意圖……………….34 圖2.6電鍍技術製作覆晶銲錫凸塊之示意圖…………………………..34 圖2.7網板印刷技術方式來製作銲錫凸塊之示意圖………………….35 圖2.8添加劑在電鍍中改變金屬離子吸附之示意圖………………….35 圖2.9 電遷移造成孔洞(Void)及凸起晶粒(Hillock)之示意圖……….37 圖2.10 電遷移造成電阻變化之三個階段……………………………..37 圖2.11 電遷移造成破壞之機制………………………………………….38 圖2.12 Buerke等人之實驗觀察方式…………………………………..38 圖2.13 Wang等人之實驗設計之示意圖………………………………..39 圖2.14 Liu等人實驗設計之示意圖…………………………………..39 圖2.15 Huynh等人實驗設計之示意圖……………………………….40 圖2.16 Lee等人實驗設計之示意圖…………………………………..40 圖2.17 Lee等人實驗設計之示意圖…………………………………..41 圖2.18 Yeh等人實驗設計之示意圖…………………………………..41 圖2.19 Ye等人實驗設計之示意圖……………………………………42 圖2.20 Ye等人實驗設計之示意圖…………………………………….42 圖2.21 Chen等人實驗設計之示意圖………………………………….43 圖2.22 晶粒中之三晶界交叉點之示意圖………………………………27 圖2.23 不同晶界夾角之示意圖…………………………………………..29 圖3.1實驗流程圖…………………………………………………………..52 圖3.2電鍍錫鋅合金及電鍍鉍之研究流程圖…………………………..53 圖3.3 熱風式迴銲爐之迴銲曲線………………………………………..54 圖3.4 覆晶技術之無鉛銲錫凸塊製作流程圖………………………….55 圖3.5 覆晶技術之電鍍銲錫凸塊製程示意圖………………………….56 圖3.6 覆晶技術製程之實驗流程圖……………………………………..57 圖3.7 矽晶/凸塊/矽晶覆晶組裝之實驗示意圖………………………..58 圖3.8 覆晶組裝接點之電遷移實驗示意圖…………………………….58 圖3.9電流密度之模擬分析實驗之結構示意圖………………………..59 圖4.1不同硫酸鋅濃度的鍍液所電鍍錫鋅合金之表面型態 (a); (b); (c); (d) ……………………………………………………………..62 圖4.2不同電流密度所電鍍錫鋅合金之表面型態 (a); (b); (c); (d) ……………………………………………………………..63 圖4.3不同硫酸鋅濃度之鍍液電鍍錫鋅合金之鋅含量…….…………64 圖4.4硫酸鋅濃度為59g/L之鍍液在不同電流密度電鍍錫鋅合金之鋅含量…………………………………………………………………………..64 圖4.5電鍍錫鋅合金之厚度與時間關係圖………………………..……65 圖4.6電鍍錫鋅合金之DSC分析………………………………………..65 圖4.7為電鍍錫鋅凸塊的表面型態………………………………………69 圖4.8錫鋅凸塊表面的微觀結構型態……………………………………69 圖4.9錫鋅凸塊迴銲前的側視圖…………………………………………69 圖4.10一般傳統鉛錫的迴銲曲線示意圖………………………….……70 圖4.11使用RMA助銲劑之錫鋅凸塊迴銲結果……………..…………71 圖4.12使用BF-31助銲劑之錫鋅凸塊迴銲結果………………………71 圖4.13錫鋅凸塊迴銲後巨觀之表面型態…………………………….…72 圖4.14矽晶片迴銲後之截面金相圖………………………………….…72 圖4.15銅墊上方之錫鋅銲錫凸塊迴銲後之截面金相圖………………73 圖4.16錫鋅凸塊迴銲後之金相組織…………………………….…….…73 圖4.17銅層與錫鋅銲錫間在迴銲後界面反應的型態…………………74 圖4.18 銅鋅之二元相圖……………………………………………….…74 圖4.19 SEM(SE)觀察下之不同電流密度所電鍍鉍表面型態 (a); (b); (c); (d) ………………………………………….…………….……75 圖4.20 電鍍鉍之厚度與時間關係圖……………………………………76 圖4.21迴銲後之錫鋅鉍凸塊…………………………………………..…77 圖4.22.錫鋅鉍凸塊之截面金相……………………………………..……77 圖4.23 電流密度為4.4×103A/cm2-120℃環境下:(a)初始;(b)32小時;(c)72小時;(d)100小時之二次電子(SE)影像………………………79 圖4.24 電流密度為4.4×103A/cm2-120℃環境下,72小時之SE影像:(a)接點上方(正極端);(b)接點下方(負極端)……….……………80 圖4.25 電流密度為4.4×103A/cm2-120℃環境下:(a)初始;(b)32小時;(c)72小時;(d)100小時之背向散射電子(BSE)影像..………………81 圖4.26 電流密度為4.4×103A/cm2-120℃環境下,72小時之BSE影像:(a)接點上方(正極端);(b)接點下方(負極端)…………………83 圖4.27 電流密度為4.4×103A/cm2-120℃環境下,100小時:(a)正極端之界面;(b)負極端之界面,其金相結果………………………………84 圖4.28 電流密度為4.5×104A/cm2-120℃環境下:(a)初始;(b)8小時;(c)16小時;(d)32小時之SE影像…………………………………………91 圖4.29 電流密度為4.5×104A/cm2-120℃環境下:(a)初始;(b)8小時;(c)16小時;(d)32小時之BSE影像………………………………………92 圖4.30 銅層與介金屬化合物(IMC1)間之凸起化合物(IMC2),在正極端有擠出之現象………………………………………………………94 圖4.31 電流密度為4.5×104A/cm2-120℃環境下,8小時之SE影像:(a)接點上方(正極端);(b)接點下方(負極端)…….………………95 圖4.32 電流密度為4.5×104A/cm2-120℃環境下,8小時之BSE影像:(a)接點上方(正極端);(b)接點下方(負極端)……….……………96 圖4.33 電流密度為4.5×104A/cm2-120℃環境下,32小時之BSE影像:(a)接點上方(負極端);(b)接點下方(正極端)……..…………97 圖4.34 電流密度為4.5×104A/cm2-120℃環境下,32小時之BSE影像:(a)接點上方(正極端);(b)接點下方(負極端)…….…………98 圖4.35 電流密度為4.5×104A/cm2-120℃環境下,32小時之正極端界面:(a)SE;(b)BSE之影像……………………………………………..…99 圖4.36 銲錫基地之隆起現象:(a)SE;(b)BSE影像………..…………101 圖4.37 初始接點之電流密度分佈……………………………………………102 圖4.38 銲錫基地中,表面之介金屬化合物的形貌:(a)SE;(b)BSE影像…………………………………………………………………………103 圖4.39 無電流-120℃下,8小時之金相:(a)SE;(b)BSE;(c)上端界面之SE影像;(d)上端界面之BSE影像………………………………104 圖4.40 無電流-120℃下,32小時之金相:(a)SE;(b)BSE;(c)上端界面之SE影像;(d)上端界面之BSE影像……………………..……105 圖4.41 無電流-120℃下,32小時,研磨表面後之金相:(a)SE;(b)BSE;(c)上端界面之SE影像;(d)上端界面之BSE影像;(e)下端界面之SE影像;(f)下端界面之BSE影像……………………………107 圖4.42 電流密度為4×103A/cm2-120℃下,般100小時,研磨表面後之金相:(a)SE;(b)BSE;(c)上端界面(正極端)之SE影像;(d)上端界面之BSE影像;(e)下端界面(負極端)之SE影像;(f) 下端界面之BSE影像……………………………………………………………..108 圖4.43 電流密度為1.0×104A/cm2-120℃下,界面處的微裂縫之成長金相:(a)初始;(b)8小時;(c)16小時;(d)32小時之SE影像…..111 圖4.44 電流密度為1.0×104A/cm2-150℃環境下:(a)初始之SE影像;(b)初始之BSE影像;(c)6小時之SE影像;(d)6小時之BSE影像 ……………………………………………………………………………….112 圖4.45 電流密度為1.0×104A/cm2-150℃下,6小時之SE影像:(a)接點上方(負極端);(b)接點下方(正極端)………………………113 圖4.46 電流密度為1.0×104A/cm2-150℃下,6小時,研磨表面後之金相:(a)SE;(b)BSE;(c)上端界面(負極端)之SE影像;(d)上端界面之BSE影像;(e)下端界面(正極端)之SE影像;(f) 下端界面之BSE影像…………………………………………………………………………114 圖4.47 電流密度為1.0×104A/cm2-150℃下,6小時,銲錫基地之金相:(a)SE影像;(b)BSE影像……………………………………….…115 圖4.48 電流密度為4.5×104A/cm2-120℃環境下,72小時之BSE影像. ……………………………………………………..……………………118 圖4.49 微裂縫生成之結構示意圖……………………………………………118 圖4.50 微裂縫在界面生成後之電流密度分佈……………………….………119 圖4.51 電流密度為4.5×104A/cm2-120℃下,117小時後,接點失效之金相:(a)500×;(b)1000×之SE影像……………………………………120 表 目 錄 表2.1 常見無鉛銲錫………………………………………………………36 表4.1 電流密度為4.4×103A/cm2-120℃環境下,不同時間下介金屬化合物之組成成份………………………………………………………….…82 表4.2 電流密度為4.5×104A/cm2-120℃環境下,不同時間下介金屬化合物之組成成份…………………………………………………….………93 表4.3 C1接點在電流密度為4.5×104A/cm2-120℃環境下,介金屬化合物各位置之組成成份……………………………………………….…100 表4.4 C2接點在電流密度為4.5×104A/cm2-120℃環境下,介金屬化合物各位置之組成成份…………………………………………….……100 表4.5 無電流-120℃下,介金屬化合物之組成成份…………………106 表4.6 電流密度為4×103A/cm2-120℃下,100小時,研磨表面之金相後介金屬化合物的組成成份………………………………………….…109 | |
dc.language.iso | zh-TW | |
dc.title | Sn-8Zn-3Bi覆晶組裝製程及其電遷移研究 | zh_TW |
dc.title | Electroplating Process and Electromigration Effect of Sn-8Zn-3Bi Flip Chip Bumps | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 林昭松,楊申語,楊智富,蔡顯榮,李義剛,江東昇,張世穎 | |
dc.subject.keyword | 無鉛銲錫,電子構裝,電鍍,電遷移, | zh_TW |
dc.subject.keyword | lead-free solder,electronics packaging,electroplating,electromigration, | en |
dc.relation.page | 135 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-13 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
顯示於系所單位: | 材料科學與工程學系 |
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