低功率大型乘法器高階數位電路之功率最佳化

Abstract

由於矽積體電路製程的特徵及尺寸縮小到深次微米元件，現今積體電路設計 的技術，可將更多電路集合在單一晶片上，而這麼多元件在同一個晶片上面，不僅電路設計上變複雜，要維持電路有良好的效能，最重要必須考慮到的就是功率消耗的問題。 這篇論文裡，我們主要是探討新的邏輯閘層級兩個臨界電壓最佳化靜態功率 方法(novel gate-level dual-threshold static power optimization methodology；GDTPOM)這個演算法，這個演算法是利用Synopsys PrimeTime工具以及靜態時序分析(static timing analysis)的方法，針對用90nm MTCMOS的製程設計一個速度快、功率消耗小的晶片系統。在我們分析的過程中，主要是使用到裡面高臨界電壓以及低臨界電壓的標準元件資料庫(cell library)，因為高臨界電壓的標準元件資料庫優點是具有較低的消耗功率，而低臨界電壓的標準元件資料庫優點是具有較快的操作速度。我們先設計一個16 bits乘法器的數位電路，利用兩個不同臨界電壓的標準元件資料庫來分析，使用新思(synopsys)公司所開發的PrimeTime工具加入靜態時序分析方法來達到我們所希望電路速度的要求，並且利用此最佳化16bits乘法器的結果結合成超大型32bits乘法器電路。實驗結果發現不僅16 bits或32 bits乘法器與全部都由低臨界電壓cell組成的電路比較，都可以在電路速度要求下達到將近50%的leakage power消耗。

As integrated-circuit (IC) technology advances to into deep-submicron (DSM) regime, more functionality can be combined into a single chip. To design such a complex device, low power consumption has become a significant requirement. If you want to design a high performance circuit, you should keep power consumption. The paper describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique using Synopsys PrimeTime tool for designing high-speed low-power SOC applications dealing with 90nm MTCMOS technology. The cell libraries come in fixed threshold - high Vt for low static power and low Vt for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library. And then we get the optimized 16 bits multiplier to combined a large size 32 bits multiplier. We can get the good result ─ 50% less leakage power consumption using 16 bits or 32bits multiplier.