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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37798完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Vincent Su | en |
| dc.contributor.author | 蘇文生 | zh_TW |
| dc.date.accessioned | 2021-06-13T15:44:22Z | - |
| dc.date.available | 2013-07-07 | |
| dc.date.copyright | 2008-07-07 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-02 | |
| dc.identifier.citation | Chapter 2
[2.1] P. C. Fazan and V. K. Mathews, “A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs,” IEDM Dig.,, 57-60 (1993). [2.2] Taurus TSUPREM-4 User Guide, Synopsys Inc., Mountain View, CA, 146 Oct. 2005. Chapter 3 [3.1] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., 2002, pp. 117–120. [3.2] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical Analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1254–1261, Aug. 2004. [3.3] J. Pretet, D. Ioannou, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Narrow-channel effects and their impact on the static And floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs,” Solid State Electron., vol. 46, no. 11, pp. 1699–1707, Nov. 2002. [3.4] J. Pretet, N. Subba, D. Ioannou, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Reduced floating body effects in narrow channel SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, no. 1, pp. 55–57, Jan. 2002. [3.5] Lin I, Su V, Kuo J, Lee R, Lin G, Chen D, Yeh C, Tsai C, Ma M,“Influence of STI-Induced mechanical stress in kink effect of 65nm PD SOI CMOS devices, ” EDSSC 2007; 107-108. [3.6] I. Lin, V. Su, J. B. Kuo, M. Ma, C. T. Tsai, C. S. Yeh and D. Chen,“STI Mechanical Stress Induced Subthreshold Kink Effect of 40nm PD SOI NMOS Device,” Dig. Of ISDRS, Washington, Dec. 2007. [3.7] V. C. Su, I. S. Lin, J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai and M. Ma, “Shallow Trench Isolation (STI)-Induced Mechanical Stress-Related Kink Effect Behavior of 40nm PD SOI NMOS Device,”to be published in IEEE Trans. Electron Devices, June 2008. [3.8] Lin IS, Su VC, Kuo JB, Chen D, Yeh CS, Tsai CZ, Ma M, “STI-induced mechanical stress-related kink effect of 40nm PD SOI NMOS devices, ”EUROSOI 2008; 81-82. [3.9] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. [3.10] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984. [3.11] J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gain model for BJT devices operating at 77 K,” Solid State Electron., vol. 35, no. 6, pp. 785–790, Jun. 1992. Chapter 4 [4.1] Y. G. Chen, S. Y. Ma, J. B. Kuo and R. W. Dutton, “An Analytical Drain Current Model for Short-Channel FD Ultrathin SOI NMOS Devices,” Solid State Electronics, Vol. 38, pp. 2051-2057, 1995. [4.2] K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEE Trans. Electron Devices, Vol. 44, No. 2, pp. 324-330, Feb. 1997. [4.3] J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gain model for BJT devices operating at 77 K,” Solid State Electron., vol. 35, no. 6, pp. 785–790, Jun. 1992. [4.4] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984. [4.6] E. V. Ploeg, C.T. Nguyen, S. S. Wong and J. D. Plummer, “Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 41, pp. 970-977, 1994. [4.7] J. Y. Choi, J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicormeter SOI MOSFET’S,”IEEE Trans. Electron Devices, Vol. 38, pp. 1384-1391, 1991. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37798 | - |
| dc.description.abstract | 本篇論文研究淺槽隔離引起機械壓力對於奈米級部分解離絕緣體上矽金氧半元件崩潰效應模型分析。第二章簡介機械壓力的重要性。第三章藉由量測資料與模擬的結果，得知對於源極/集極長度(S/D L)較短者其崩潰電壓會比較大。主要的原因在於機械壓力引起能隙縮小使得寄生雙載子電晶體性能變差，即使源極/集極長度較短者其後夾止區域(post-pinchoff region)所產生的撞擊游離更嚴重，仍然無法抑制住寄生雙載子電晶體性能變差的效應。第四章推導精簡的崩潰電壓模型，並且將模型結果與模擬結果和量測數據比較，證明崩潰電壓模型的正確與精確性。並有說明部分解離絕緣體上矽金氧半元件因存在浮動基體，所以撞擊游離與寄生雙載子電晶體互相影響牽制，此特性與一般矽金氧半元件特性完全不同。第五章為總結。 | zh_TW |
| dc.description.abstract | This thesis reports the shallow-trench-isolation (STI)-induced mechanical-stress-related breakdown behavior of the nanometer PD-SOI NMOS device. Chapter 2 introduces the STI-induced mechanical stress. In chapter 3, as verified by the experimentally measured data and the 2D simulation results, the breakdown voltage becomes higher for the device with a smaller S/D length due to the weaker function of the parasitic bipolar device, offset by the stronger impact ionization in the post-pinchoff region. Chapter 4 derives the compact breakdown model. As verified by the experimentally measured data and the 2D simulaiton results, this compact breakdown model provides an accurate prediction. However, unlike the bulk MOSFET, the SOI MOSFET body floats due to the buried oxide structure and results in feedback mechanism between the impact ionization multiplication that takes place in the high-field region near the drain and the current gain of the parasitic bipolar structure. Chapter 5 is the conclusion of this research. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T15:44:22Z (GMT). No. of bitstreams: 1 ntu-97-R95943141-1.pdf: 1821186 bytes, checksum: 7899e1506635aa4c1361a7043f8c580b (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Chapter 1 導論 1
Chapter 2 淺槽隔離引起機械壓力 5 2.1 簡介 5 2.1 淺槽隔離的製程技術 5 2.3 機械壓力模擬 7 2.4 參考文獻 8 Chapter 3 模擬機械壓力對於奈米級部分解離絕緣體上矽N型金氧半元件之崩潰行為 12 3.1 簡介 12 3.2 模擬驗證 13 3.3 討論 15 3.4 結論 18 3.5 參考文獻 19 Chapter 4 機械壓力對於奈米級部分解離絕緣體上矽N型金氧半元件之崩潰精簡模型 27 4.1 簡介 27 4.2 模型推導 28 4.2.1 飽和區電流傳導機制 28 4.2.2 飽和區汲極電流模型 29 4.2.3 精簡崩潰電壓模型 31 4.3 模型驗證 34 4.4 討論 35 4.5 結論 38 4.6 參考文獻 38 Chapter 5 總結 47 | |
| dc.language.iso | zh-TW | |
| dc.subject | 機械壓力 | zh_TW |
| dc.subject | 絕緣體上矽金氧半 | zh_TW |
| dc.subject | 淺槽隔離 | zh_TW |
| dc.subject | 崩潰 | zh_TW |
| dc.subject | mechanical stress | en |
| dc.subject | breakdown | en |
| dc.subject | shallow trench isolation | en |
| dc.subject | SOI MOS | en |
| dc.title | 淺槽隔離引起機械壓力對於奈米級部分解離絕緣體上矽金氧半元件崩潰效應模型分析 | zh_TW |
| dc.title | Analysis and Modeling of STI-Iduced Mechanical Stress-Related Breakdown Behavior For Nanometer PD-SOI MOS Devices | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡成宗,林吉聰,陳正雄 | |
| dc.subject.keyword | 淺槽隔離,崩潰,機械壓力,絕緣體上矽金氧半, | zh_TW |
| dc.subject.keyword | shallow trench isolation,breakdown,mechanical stress,SOI MOS, | en |
| dc.relation.page | 48 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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