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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37320
標題: | 超大型積體電路精確壓縮的閘時序模型和有效率的時序模擬演算法 VLSI Compact and Accurate Gate Timing Modeling and Efficient Timing Simulation Algorithm |
作者: | Jian-Feng Chen 陳健峰 |
指導教授: | 陳中平(Chung-Ping Chen) |
關鍵字: | 電流源模型,資料壓縮,閘延遲,內部連線延遲,時序分析,遞迴卷積,電路模擬, Current Source Model,Data compression,Gate delay,Interconnect delay,Timing analysis,Recursive convolution,Circuit simulation, |
出版年 : | 2008 |
學位: | 碩士 |
摘要: | 靜態時序分析對奈米積體電路設計過程中是很重要的ㄧ環。在加快靜態時序分析速度的時候而準確度必須同時要兼顧。這篇論文主要針對靜態時序分析的兩個重要部份做探討,並對這些問題提出方法來解決。第一部份主要是要如何有效及精確的得到所有標準邏輯元件的行為模型。隨著標準邏輯元件越來越多,為了要維持準確度,大量的模擬資料需要被儲存起來,這勢必要耗費大量的記憶體空間,所以為了解決這些問題我們提出了壓縮資料方法。這方法壓縮率可以達19X並且空間節省95%,提高壓縮率的同時還維持該有的精確度。第二部份,先進製程中由於IC內部連線高阻抗導致其延遲主宰了整個電路的延遲。然而內部連線的寄生電容和電感所增加的效應影響信號的品質而且也提高了計算時的複雜度。針對這幾點我們提出快速遞迴卷積 (fast recursive convolution) 方法模擬。經過實驗發現最後的結果準確度很高,最後結果跟SPICE比較誤差小於1%,速度也比SPICE快一千倍。 Static Timing Analysis (STA) is very important for nanometer integrated circuit design. The accuracy of STA still needs to be improved while minimizing runtime penalty. This thesis focuses on two important aspects of STA. First, an efficient and accurate method is needed for obtaining the behavior model of all standard cells. With the existing large number of standard cells, a substantial amount of simulation data has to be recorded to maintain the accuracy. This in turn results in an unbearable amount of memory overhead. We present a method to compress the large gate timing information, to minimize the amount of memory overhead. A compression ratio of 19X and a Space Saving of 95% can be achieved and the compacted data still maintained a very high level of accuracy. Second, the interconnect delay dominates the circuit path delay for today's CMOS technology due to the effect of the high impedance interconnect. However, parasitic capacitance and inductance in interconnections have begun to increasingly affect the signal quality and the computed complexity. We present a new fast recursive convolution method for timing simulation. Experimental results show very accurate result of 1% error and one thousand times faster runtime when compared with SPICE. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37320 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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