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標題: | 應用於無線區域網路頻帶之金氧半場效電晶體低雜訊放大器之研製 Design and implementation of CMOS low noise amplifiers for WLAN frequency-band applications |
作者: | Chieh-Min Lo 羅玠旻 |
指導教授: | 王暉 |
關鍵字: | 金氧半場效電晶體,低雜訊放大器,射頻電路, CMOS,LNA,RFIC, |
出版年 : | 2005 |
學位: | 碩士 |
摘要: | 中文摘要
在這論文中,我們利用金氧半互補式(CMOS)製程來設計及實現了三個低雜訊放大器。低雜訊放大器在射頻前端系統中是一個很重要的元件。它將從天線端接之微弱的射頻信號放大而加導入較少的雜訊。傳統應用於微波及毫米波低雜訊放大器通常利用高效能及高成本之砷化鎵或磷化銦之高電子移動率電晶體/異質接面雙極電晶體製程來實現,然而卻使用較大之晶片面積。在最近幾年,由於電晶體之大小比例縮小使得CMOS的射頻效能提升且製程技術漸趨發展成熟,而其單位電流增益頻率提升到已經能與砷化鎵製程相比較之等級。此外,CMOS製程能和數位電路整合,是未來系統整合在晶片上很好的選擇。 利用台積電0.18um CMOS之製程,我們設計了5-6 GHz的低雜訊放大器及增益可變式之低雜訊放大器。我們利用了螺旋堆疊式電感在較小的晶片面積下達成效能可接受的品質因數及自我共振頻率。5-6 GHz低雜放大器量測之最低雜訊指數為2.6 dB。另一個低雜訊放大器,利用電流導向之架構,來達成增益可控制之功能。利用電流導向來控制增益可達到超大之增益控制範圍約40 dB。此外,一級之可增益式低雜訊放大器在高增益下之量測的雜訊指數為2.7 dB。 除了上述二個設計在微波頻段之低雜訊放大器,我們也利用台積電0.13um 射頻及混合信號CMOS製程設計了一個應用在毫米波頻段 (V頻帶)之低雜訊放大器。量測出來之小信號增益是目前發表在毫米波頻段中之CMOS低雜訊放大器中增益最高的。在電路設計中,我們利用薄膜微帶線(Thin-film microstipline)來實現阻抗匹配電路。在50-57 GHz,量測出來之增益至少20 dB,雜訊指數約8 dB,且晶片大小只有0.42 mm2。 In this thesis, three low noise amplifiers (LNAs) are designed, and implemented using CMOS process. LNA is the critical component in the RF front-end circuits. It amplifies the weak RF signal from the antenna with minimum noise contribution. The conventional LNAs for microwave and millimeter-wave applications were usually implemented with high-cost and high-performance technology, GaAs or InP HEMT/HBT with large chip sizes. In recent years, the RF CMOS technology becomes mature with scaling down size of MOSFET, such that the fT in MOSFET is comparable to that in GaAs technology. Besides, the feature of CMOS such as higher integration capability with digital circuits is attractive for the system-on-chip (SOC) development. A 5-6 GHz low noise amplifier and variable gain low noise amplifier (VGLNA) are designed and implemented using TSMC 0.18um standard CMOS process. By using helix-stacked inductors, an acceptable quality factor and self-resonate frequency are achieved with a smaller chip size. The noise figure of LNA is measured with minimum value about 2.6 dB. Another LNA, featured with current steering architecture, is implemented as a VGLNA. The ultra-wide control range about 40 dB is achieved by current steering. The VGLNA exhibits a low noise figure of 2.7 dB in the high-gain mode for one-stage design. Besides the LNAs designed for microwave application, the millimeter-wave (V-band) CMOS LNA has been designed, measured and fabricated in TSMC 0.13um RF/MM CMOS process. It exhibits the highest gain among previously published CMOS amplifiers in the millimeter-wave frequency range. Thin-film microstripline is used for the impedance match of the circuit design. The V-band CMOS LNA exhibits small signal gain over 20 dB from 50 to 57 GHz and noise figure of 8 dB with chip size of only 0.42 mm2. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36261 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
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