矽晶圓薄化技術之研究

Abstract

摘要 本論文針對新興科技所需矽晶圓(Silicon Wafer)基材Substrate)之薄化製造技術，提出系統性的研究分析，並藉此開發出可供產業界應用的具體模式。由於電子產品的微小化是長年的發展趨勢，過去的足跡及未來的走向均十分明確；如何使最後封裝完成的構件，具備最小的空間與最大積體電路(IC)元件密度將是主要的關鍵技術。在縮小封裝厚度的方法上，IC電子元件在線寬及厚度已到了縮小的極限，為了更進一步實現封裝尺寸的縮小，就有必要減少矽晶片(Chip)的厚度。然而在最終封裝矽晶片厚度變薄之際，相對的矽晶圓直徑由8吋增加到12吋的厚度卻相反的變得更厚，因此有必要開發具有前瞻性的矽晶圓薄化加工技術，才能夠符合先進矽晶片封裝嚴苛工程規格之要求。 本研究首先以矽晶圓延性輪磨加工的理論基礎，延伸其應用於薄化技術的開發。探討輪磨加工所伴隨的殘留應力，以及矽晶圓次表面破壞層(SSD)的問題，終究其薄化目標將碰觸到極限。本研究構思以濕式化學蝕刻的結合，一方面藉以去除次表面破壞層及輪磨加工所衍生的殘留應力，一方面則繼續推進矽晶圓薄化在工程尺寸的極限。本項製程技術的開發除著眼於工程規格之要求外，產業實用性同時是考量的主軸。 本研究針對矽晶圓殘留應力理論模型，及其實驗量測進行深入研究。由矽晶圓薄化後的強度與翹曲狀況，分析殘留應力與各參數之相關性，以達成矽晶片切割與封裝後的高可靠度與產品壽命提昇。同時為確保矽晶圓背面在金屬蒸鍍(Evaporation)後，不致產生剝落(Peeling)現象，矽晶圓薄化時之表面性質與粗度控制是本研究另一發展重點。 關鍵字：矽晶圓、薄化、濕式化學蝕刻、殘留應力。

Abstract Silicon wafers are most extensively used materials for integrated circuit (IC) substrates. As the demand of miniaturization with higher performance standards for electronic devices such as memory cards, smart cards, portable communication devices, and portable computers becomes a clear trend. IC package makes it a requirement to reduce both feature sizes and chip thickness. These requirements render the chip and packaging designers to develop high-speed, ultra-thin chips that utilize less individual area and overall package height to accommodate multiple layers of dense interconnects. The chips that are required to fit into these more intelligent devices have to be remarkably thin, which indicates that silicon chip thinning and stress relief considerations are becoming more significant issues in the backend and assembly areas of semiconductor component manufacturing. In this research, experimental observations are conducted to investigate the effects of various parameters on the surface finish and subsurface damage (SSD) of ground silicon wafers. As there are more technological advancements in stacked chip packaging, backside wafer surface conditioning and stress relief applications become an essential focus. Using wet chemical etching technology for wafer thinning not only provides a means of strength enhancement but allows the user to control the backside wafer surface finish. Various degrees of backside wafer surface finish can be achieved with aqueous chemical etchants. Because the roughened backside wafer surface can be created with the introduced chemicals, it is found that no propagating crystalline defects are accompanied, but rather leaves the wafer in an optimum state for back metal adhesion. Other crucial item in the study is to investigate the residual stress on the backside surface. The technology of wafer thinning is well tested, and the process fine tuned. The goal of compiling a specific database for the thinning process is finally achieved. Keywords: Silicon Wafer, Thinning, Wet Chemical Etching, and Residual Stress.