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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36058完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳恩柏 | |
| dc.contributor.author | Tsrong-Yi Wen | en |
| dc.contributor.author | 溫琮毅 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:50:31Z | - |
| dc.date.available | 2010-07-28 | |
| dc.date.copyright | 2005-07-28 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-25 | |
| dc.identifier.citation | [1] Eichelberger and C. William, “Single Chip Modules, Repairable Multichip Modules, and Methods of Fabrication Thereof,” Nov. 24, 1998, US PATENT 5841193
[2] http://www.intel.com/pressroom/archive/releases/20011008tech.htm http://www.intel.com/pressroom/archive/backgrnd/20011008tech_bkgrd.htm [3] S.N. Towle, H. Braunisch, C. Hu, R.D. Emery and G.J. Vandentop, “Bumpless Build-Up Layer Packaging,” in Proc. ASME Int. Mech. Eng. Congress and Exposition(IMECE), New York, Nov. 11-16, 2001, paper no. EPP-24703, 7 pages on CD-ROM. [4] C.Y. Liu, J. Swan, S. Towle and A. George, “Thinned Die Integrated Circuit Package,” Jan. 11, 2005, US PATENT 6841413 [5] H. Braunisch, S.N. Towle, R.D. Emery, C. Hu and G.J. Vandentop, “Electrical Performance of Bumpless Build-Up Layer Packaging,” Electronic Components and Technology Conference, 2002. Proceedings. 52nd, 28-31 May 2002 Page(s):353 – 358 [6] E. Jung, A. Ostmann, D. Wojakowski, C. Landesberger, R. Aschenbrenner and H. Reichl, “Ultra Thin Chip for Miniaturized Products”, Polymers and Adhesives in Microelectronics and Photonics, 2001. First International IEEE Conference on 21-24 Oct. 2001 Page(s):236 – 240 [7] E. Jung, D. Wojakowski, A. Neumann, C. Landesberger, A. Ostmann, R. Aschenbrenner and H. Reichl, “Chip-in-Polymer: Volumetric Packaging Solution using PCB technology”, Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International, 17-18 July 2002 Page(s):46 – 49 [8] Nathan, J. Richard, Shepherd and H. William, “Integrated Package and Methods for Making Same,” Mar. 4, 2003, US PATENT 6528351 [9] Asahi, Toshiyuki, Sugaya, Yasuhiro, Komatsu, Shingo, Nakatani and Seiichi, “Component Built-In Module and Method of Manufacturing The Same,” Dec. 3, 2002, US PATENT 6489685 [10] B.A. Zahn, “Evaluation of Simplified and Complex Thermal Finite Element Models for a 3-Die Stacked Chip Scale Ball Grid Array Package,” Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International, Jul 14-16, 2004 Page(s):106 – 112 [11] 陳文華, 鄭仙志, 鍾宜君, 林書如, 林志翰, “三維多晶片模組電子構裝之熱效能與可靠度研究,” 第二十屆機械工程研討會, 2003 [12] J.T. Cook, Y.K. Joshi and R. Doraiswami, “Interconnect Thermal Management of High Power Packaged Electronic Architectures,” Semiconductor Thermal Measurement and Management Symposium, 2004. Twentieth Annual IEEE, 9-11 Mar 2004 Page(s):30 – 37 [13] J.P Holman, “Heat Transfer,” 8th SI Edition, McGrawHill, New York, 2001 [14] G.N. Ellison, “Thermal Computation for Electronic Equipment,” Van Nostrand Reinhold, New York, 1984 [15] S. Moaveni, “Finite Element Analysis – Theory and Application With Ansys”, 2nd Edition, Prentice Hall, New Jersey, 2003 [16] G. Ridsdale, J. Bennett, J. Bigler and V.M. Torrers, “Thermal Simulation to Analyze Design Features of Plastic Quad Flat Package,” Int. J. Microcircuits Electron. Packaging, 1996, Vol. 19, pp. 103–109. [17] 陳珮儀, “無電鍍銅在Ta(N)阻隔層上成核與成長之研究,” 國立清華大學碩士論文,2001 [18] 鄧經緯, “濕式活化無電鍍銅技術在Ta(N)阻隔層上金屬化之研究,” 國立清華大學碩士論文,2001 [19] 洪源德, “以無電電鍍技術沈積鎳/銅凸塊與銲錫和鎳銅之界面反應研究,” 國立交通大學碩士論文, 2002 [20] H. Xiao, “Introduction to Semiconductor Manufacturing Technology,” Prentice Hall, New Jersey , 2001 [21] EIA/JESD51, “Methodology for the Thermal Measurement of Component Packages(Single Semiconductor Device),” Electronic Industries Association, 1995 [22] EIA/JESD51-1, “Integrated Circuit Thermal Measurement Method – Electrical Test Method(Single Semiconductor Device),” Electronic Industries Association, 1995 [23] EIA/JESD51-2, “Integrated Circuit Thermal Test Method Environment Conditions – Natural Convection(Still Air),” Electronic Industries Association, 1995 [24] “User Manual – Flip Chip Thermal Chip(FCTHCP),” 工研院電子所 [25] M.F. Modest, “Radiative Heat Transfer,” McGrawHill, New York, 1993 [26] http://www.electronics-cooling.com/Resources/EC_Articles/SEP96/sep96_02.htm [27] A. Faghri, “Heat Pipe Science and Technology,” Taylor and Francis, 1995 [28] Zuo, Jon, Ernst and M. Donald, “Semiconductor Package with Lid Heat Spreader,” Feb. 22, 2005, US PATENT 6858929 [29] http://www.electronics-cooling.com/Resources/EC_Articles/SEP96/sep96_04.htm [30] 徐德勝, “半導體製冷與應用技術,” 上海交通出版社, 1999 [31] Leija, M. Javier, Lucero and D. Christopher, “Cooling System for An Electronic Component,” Apr. 19, 2005, US PATENT 6880345 [32]邱瑞易, “積體化熱電元件-致冷器之設計與分析,” 國立中興大學碩士論文, 2003 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36058 | - |
| dc.description.abstract | 封裝是為了提供晶片(Chip)保護及支承。也因為如此,晶片被封裝的材料包覆而使得熱量不容易散去,使封裝體中的各種材料產生熱應力的不匹配而造成多種破壞模式。因此,解決封裝體的散熱問題是刻不容緩的。
本文主旨在於討論一種新式構裝結構的散熱問題-基板內埋晶片封裝(Chip in Substrate, CiSP)。首先以有限元素法模擬分析現有的有機基板內埋晶片封裝在自然對流條件下的散熱能力,從中理出一些可以增進散熱效能的想法,包括使用較高熱傳導係數的材料,縮短熱傳導的距離與增加熱傳導的途徑。利用這些想法,我們設計出另一種新式金屬基板內埋晶片封裝的結構。透過金屬的強大熱傳導係數可以將熱量從晶片快速的帶至基板中再散至外界,並且將線路直接由晶片的銲墊往外延伸以降低封裝的整體厚度,使得熱傳導的距離降低,以達到有效散熱的目的。 透過簡單的製程本文將設計的金屬基板內埋晶片構裝實現出來,並且利用標準的實驗規範與設備實際量測其晶片接面溫度與熱阻。同時驗證各種不同數值模擬的邊界條件與實驗值之間的差異,結果發現同時考慮水平及垂直面的邊界條件,且配合Ellison的對流以及Ridsdale的輻射公式所得到的結果與實驗值最為接近。因此在透過這套方法繼續模擬且討論一些參數的變化,包括錫球數目的多寡以及不同發射係數對於散熱造成的影響。 最後整理我們一連串的分析,我們知道邊界條件對於數值模擬的影響最大。除此之外,我們也建立了簡化與原始線路的模型並且互相比較發現,模型的準確性也會影響模擬的結果,因此建立正確且精準的模型對於熱傳分析也是必要的。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:50:31Z (GMT). No. of bitstreams: 1 ntu-94-R92543041-1.pdf: 1422939 bytes, checksum: 3953882fe4bc705459cdf4351b1fa560 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 摘要 I
目錄 II 圖目錄 III 表目錄 VII 第一章、緒論 1 1-1 研究背景與動機 1 1-2 文獻回顧 5 第二章、基板內埋晶片構裝之熱傳數值分析 6 2-1 引言 6 2-2 熱傳數值模擬簡介 7 2-3 有機基板內埋晶片構裝熱傳數值分析 14 2-4 金屬基板內埋晶片構裝數值分析 30 2-5 討論與結語 42 第三章、金屬基板內埋晶片構裝製程設計、實做與量測 45 3-1 引言 45 3-2 金屬基板內埋晶片構裝製程設計與討論 46 3-3 金屬基板內埋晶片構裝實體尺寸與模型建立 56 3-4 金屬基板內埋晶片構裝實驗量測與分析 60 3-5 結語 72 第四章、基板內埋晶片構裝模擬與實驗綜合討論 74 4-1 引言 74 4-2 數值模擬誤差與討論 75 4-3 增強基板內埋晶片構裝散熱性能之前瞻技術討論 80 4-4 結語 87 第五章、結論與未來展望 89 5-1 結論 89 5-2 未來展望 91 參考文獻: 93 | |
| dc.language.iso | zh-TW | |
| dc.subject | 內埋式 | zh_TW |
| dc.subject | 散熱 | zh_TW |
| dc.subject | 構裝 | zh_TW |
| dc.subject | CiSP | en |
| dc.subject | package | en |
| dc.title | 基板內埋晶片構裝之設計、製程與散熱分析 | zh_TW |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 駱韋仲,林志榮,劉君愷 | |
| dc.subject.keyword | 內埋式,構裝,散熱, | zh_TW |
| dc.subject.keyword | CiSP,package, | en |
| dc.relation.page | 95 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-26 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 應用力學研究所 | zh_TW |
| 顯示於系所單位: | 應用力學研究所 | |
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