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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂學士 | |
dc.contributor.author | Wei-En Chien | en |
dc.contributor.author | 簡維恩 | zh_TW |
dc.date.accessioned | 2021-06-13T07:49:13Z | - |
dc.date.available | 2006-07-30 | |
dc.date.copyright | 2005-07-30 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-25 | |
dc.identifier.citation | [1] Farbod Behbahani, Yoji Kishigami, Asad A. Abidi, “CMOS Mixers and Polyphase Filters for Large Image Rejection” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 6, JUNE 2001
[2] Jan Crols, Michiel S. J. Steyaert, “Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 3, MARCH 1998 [3] Behzad Razavi, “RF Microelectronics” [4] James P. Maligeorgos and John R. Long “A Low Voltage 5.1-5.8 GHz Image-Reject Receiver with Wide Dynamic Range” IEEE JOURNAL OF SOLID-STATE CIRCUITS ,VOL.35, NO.12, DECEMBER 2000 [5] Yael Nemirovsky, Igor Brouk, and Claudio G. Jakobson “1/f Noise in CMOS Transistors for Analog Applications” IEEE TRANSACTION ON ELECTRON DEVICES, VOL.48, NO.5, MAY 2001 [6] Hooman Darabi and Asad A. Abidi “Noise in RF-CMOS Mixer : A Simple Physical Model” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.35, NO.1,JANUARY 2000 [7] Ranjit Gharpurey, Naveen Yanduru., Francesco Dantoni, Petteri Litmanen, Guglielmo Sirna, Terry Mayhugh, Charles Lin, Irene Deng, Paul Fontaine, and Fang Lin “A Direct-Conversion Receiver for the 3G WCDMA Standard”IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.3, MARCH 2003 [8] W. Namgoong and T.H. Meng, “Direct- conversion RF receiver design,” IEEE Trans. Commun., vol. 49, pp.518-529, Mar. 2001. [9] T. Melly, A.-S. Porret, C.C.Enz, and E. A. Vittoz, “An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers” IEEE JOURNAL OF SOLID-STATE CIRCUITS vol.36, pp.102-109, Jan. 2001 [10] D. Manstretta, R. Castello, and F. Svelto “Low 1/f noise in CMOS active mixers for direct conversion” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II, vol.48, pp.846-850, Sept. 2001 [11] A.A.Abidi, ”Direct conversion radio transceiverd for digital communications,”IEEE JOURNAL OF SOLID-STATE CIRCUITS vol.30, pp. 1399-1410, Dec.1995 [12] Behzad Razavi. “Design considerations for direct-conversion receivers”IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL.44,NO.6 JUNE 1997 [13] Behzad Razavi. “CMOS Technology Characterization for Analog and RF Design” IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE [14] Behzad Razavi. “CMOS RF Receiver Design for Wireless LAN Applications” [15] S. C. Rose, A CMOS Sub-harmonic Mixer for WCDMA, MS Thesis, UCB,2002 [16] 邱弘緯, Design and Fabrication of Low Noise and Multi-Band 5GHz RFICs,PHD Thesis, NTUEE, 2003 [17] 葉昆穎, A Low Power Monolithic RF Receiver in HBT, MS Thesis, NTUEE, 2003 [18] 藍祺漢, 5.2GHz CMOS RF Image Rejection Mixer, MS Thesis , NTUEE, 2001 [19] 唐志淳, Design of 5GHz CMOS RF Receiver Front End Circuit, PHD Thesis, NTUEE, 2001 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35988 | - |
dc.description.abstract | 本篇論文敘述適用於IEEE 802.11a的次諧波混波器,我們設計了一些次諧波混波器以驗證次諧波混頻技巧。在我們的設計中,射頻輸入訊號操作在5.8GHz而本地訊號操作頻率為2.9GHz,由於是直接降頻式接收機,射頻訊號直接被降至基頻。我們利用多相位濾波器來產生相位相差九十度的本地訊號,我們以實際下線的方式針對多相位濾波器設計技巧做探討,我們參考了相關文獻加入提高混頻器線性度的電路並利用摺疊式架構配合PMOS當作切換開關來實現所設計的混頻器,在設計輸入端線性電路時,我們亦考量了輸入阻抗匹配的問題。除此之外,為了達到次諧波混頻器亦能擁有I/Q兩訊號路徑,我們以相位插補加法器來獲得所需要的本地訊號。我們設計的這些混頻器其電壓轉換增益約略在8dB至10dB,雜訊指數約略在14至19dB,IIP3約為7至9Bm,本地與射頻訊號拒絕比例參數為-22dB至-26dB,所有的模擬均利用Spectre RF模擬軟體設計並透過國家晶片中心實作這些晶片。 | zh_TW |
dc.description.abstract | This report describes sub-harmonic mixers for 802.11a applications. We design some mixers to verify sub-harmonic mixing techniques. In our design, these circuits convert a 5.8 GHz RF signal directly to baseband using a 2.9 GHz LO frequency. We use poly-phases filter to generate quadrature LO signals. We implement some different topologies of poly-phases filters to discuss issues in poly-phases filter designation. For our mixers, we cite to some related references and use a parallel connected diode and common gate topology for its input stage and a folded PMOS switch as its switch quad. An input impedance match is concerned. Besides, to achieve I / Q two channel, the sub-harmonic mixer need octet-phases LO signals to attain this goal, only poly-phases filters couldn’t provide so many phase outputs. Therefore we utilize active phase generator to generate the necessary LO signals. These mixers have voltage conversion gain of about 7dB to 9dB, noise figure of 14 to 19 dB, LOR of -22 to -26dB and an IIP3 of 7 to 9dBm. These performances have been verified using SpectreRF simulations and taped out practically through CIC. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T07:49:13Z (GMT). No. of bitstreams: 1 ntu-94-R92943048-1.pdf: 3619208 bytes, checksum: 6189d69d73a0802ced652f40e1090ab4 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Content
Chapter 1 Introduction 1.1Motivation……………………………………………………1 1.1.1 Overview of WLAN Standard……………………………2 1.2 Thesis Organization………………………………………6 Chapter 2 Receiver Architecture 2.1 Heterodyne Receiver………………………………………7 2.2 Low – IF Receiver…………………………………… 8 2.3 Zero – IF Receiver………………………………………10 Chapter 3 Mixer Topologies 3.1 Mixer Principle……………………………………………………… 15 3.2 Standard Mixer……………………………………………18 3.3 Sub-sampling Mixer………………………………………20 3.4 Micro-Mixer…………………………………………………23 3.5 Multi-phases LO Mixer……………………………………25 3.5.1 Passive Multi-phases LO Mixer……………………26 3.5.2 Active Current Commutating Multi-phases LO Mixer……28 3.5.3 Passive Current Commutating Multi-phases LO Mixer…………………30 Chapter 4 Sub-Harmonic Mixer 4.1 Introduction………………………………………………33 4.2 Anti-parallel Connected Diode…………………………34 4.2.1 Analysis of Anti-parallel Diode Pair (APDP) …………………………35 4.2.2 Analysis of Parallel Connected MOS Pair (PCMP) ……………………38 4.3 Analysis of Sub-harmonic Mixer………………………41 4.3.1 Conversion Gain…………………………………………41 4.3.2 Inter-modulation Analysis……………………………45 1-dB Compression Point………………………………………45 Third-order Distortion………………………………… 47 Second-order Distortion………………………………… 49 4.3.3 Noise Figure analysis…………………………………50 4.3.4 LO Feedthrough……………………………………………52 LO Leakage Analysis……………………………………………54 Chapter 5 Implementation of Sub-harmonic Mixer 5.1 Poly – phase Shifter……………………………………61 5.1.1 Poly – phase Shifter Theory……………………… 61 Design Consideration……………………………………………68 Bandwidth…………………………………………………………68 Device Mismatch…………………………………………………68 Design Guide………………………………………………………69 5.1.2 Implementation of Poly-Phase Shifter………………70 5.2 Phase Shifting Adder………………………………………78 5.3 Single – to – Differential Transformer……………91 5.4 Sub-harmonic Mixer…………………………………………92 5.4.1 CMOS Differential Sub-harmonic Mixer………………92 5.4.2 CMOS I/Q Sub-harmonic Mixer…………………………113 5.5 Conclusion……………………………………………………122 Reference | |
dc.language.iso | en | |
dc.title | 次諧波混波器 | zh_TW |
dc.title | Sub-Harmonic Mixer | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 孟慶宗,林佑昇,孫台平,邱弘緯 | |
dc.subject.keyword | 射頻混頻器,直流電壓位準偏移,直接降頻,相位偏移電路,主動混頻器,金氧半混頻器, | zh_TW |
dc.subject.keyword | sub-harmonic mixing,CMOS mixer,dc offset,active mixer,direct conversion,phase shifter,RF mixer, | en |
dc.relation.page | 122 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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