以延遲鎖定迴路為基礎應用於超寬頻系統之頻率倍化器

Abstract

美國聯邦通訊委員會開放了一塊稱為”超寬頻”的頻帶，範圍從3.2GHz至10.5GHz。目前則有二個為了此頻帶所提出的架構，分別為MBOA及DS。MBOA-UWB系統應用了MB-OFDM的技術，而我們的目標為實現一個符合此應用之頻率倍化器。

此系統限制了跳頻時間必需小於9.5奈秒，這也是產生載波頻率的困難點所在。對於一個傳統的以鎖相迴路為基礎之頻率合成器而言，通常需要數百微秒才能完成鎖定，因此不適用於此系統。另一個解決方法為使用一個固定的鎖相迴路及單側頻帶混波器將由鎖相迴路輸出之頻率平移至想要的頻帶。然而，單側頻帶混波有著許多先天上的缺點像是高相位雜訊，功率消耗大，以及寄生訊號。本地端洩漏及寄生訊號會將旁頻帶干擾轉移至基頻，破壞信號品質。以上所提到的缺點都會嚴重地影響系統的效能。 而傳統的以延遲鎖定迴路為基礎之頻率倍化器僅能產生單一輸出頻率，當輸入參考頻率為固定的情況。但是MBOA-UWB系統需求三個載波頻率。我們提出了一個可以改變倍頻數的頻率倍化器。利用切換不同的回授訊號，即可改變倍頻數。因此輸出頻率即可在9.5奈秒內切換至不同的頻帶。 採用寬迴路頻寬，此頻率倍化器可達成小於9.5奈秒的鎖定時間。二組正交的訊號可由除二的操作產生。此超寬帶頻率倍化器使用了零點一八微米互補金氧半製程。供給電壓為一點八伏特，消耗了五十四毫瓦。其寄生訊號大小為-35 dBc及-110 dBc / Hz的相位雜訊，當頻率偏差為100 kHz。

The FCC has approved an unlicensed usage of spectrum from 3.2 GHz to 10.5 GHz called “ultra wide band (UWB)”. There are two proposed standards that are MBOA and DS respectively for this application. The MBOA-UWB system utilizes MB-OFDM technique. Our goal is to implement a frequency multiplier for the MBOA-UWB system. The difficulty of generating the carrier frequency arises from the stringent restriction on band-hopping time less than 9.5 ns. Conventional PLL-based frequency synthesizer usually takes hundreds of micro-seconds to settle and isn’t capable for such application. Another existing solution implements a non-switching PLL with single-side-band (SSB) mixing to shift the output frequency from the PLL to desired band. However, the SSB mixing has many inherent drawbacks such as high phase noise, high power, and spurious tones. The LO leakage and the unwanted sideband translate adjacent interferences to the baseband and corrupt the signal at the desired channel. All foregoing non-ideal effects degrade the performance of the UWB transceivers severely. A traditional DLL-Based frequency multiplier can only generate single one output frequency while the input frequency is fixed, whereas the UWB system demands three carrier frequencies. A modified DLL-based frequency multiplier can change the multiplication factor of the reference frequency. By switching the feedback clock from one delay cell to another, the equivalent number of delay cells is changed, and the output frequency will hop to a different band within 9.5 nSec. This frequency multiplier with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The quadrature I and Q signals are generated by a divide-by-2 operation. The UWB frequency multiplier has been fabricated in a 0.18-