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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35770完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Chi-Hsin Wang | en |
| dc.contributor.author | 王啟欣 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:09:15Z | - |
| dc.date.available | 2010-08-01 | |
| dc.date.copyright | 2005-08-01 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-26 | |
| dc.identifier.citation | [1] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons,
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Gray, 'Dithering and Its Effects on Sigma-Delta and Multi-Stage Sigma-Delta Modulation,' IEEE Proc. ISCAS, pp.368-371, May 1990. [14] I. Fujimori, L. Longo, and A. Hairapetian, 'A 90-dB SNR 2.5-MHz Output Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at 8x Oversampling Ratio,' IEEE J. Solid-State Circuits, vol. 35, no.12, pp.1820-1828, December 2000. [15] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, Kluwer Academic Publishers, 1999. [16] Hairapetian, G. C. Temes, and Z. X. Zhang, 'Multibit Sigma-Delta Modulator with Reduced Sensitivity to DAC Nonlinearity,' IEEE Electron. Lett., vol. 27, no.11, pp.990-991, May 1991. [17] L. R. Carley and J. Kenney, 'A 16-bit 4’th Order Noise-Shaping D/A Converter,' Proceedings of the 1988 IEEE Custom Integrated Circuits Conferences, pp.21.7.1-21.7.4, Rochester, NY, May 1988. [18] G. Franklin, J. Powell, and A. Emami-Naeini, Feedback Control of Dynamic Systems, Addison-Wesley Publishing Company, New York, 1994. [19] S. Hein and A. Zakhor, 'On the Stability of Sigma Delta Modulator,' IEEE Trans. on Signal Proc., vol. 41, no. 7, pp. 2322-2348, July 1993. [20] F. Chen and B. Leung, A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging,' IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 453-460, April 1995. 87 [21] L. Williams and B. Wooley, A Third-Order Sigma-Delta Modulator with Extended Dynamic Range IEEE J. Solid-State Circuits, vol. 29, no. 3, pp.193-202, March 1994. [22] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2001. [23] Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Kluwer Academic Publishers, Boston, 2002. [24] K. D. Chen, 'Automatic Coefficients Synthesis and Circuit Implementation Techniques of High-Order Sigma-Delta Modulators,' Ph.D. Thesis, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, June, 2000. [25] T. C., Hsueh, 'The Design and Implementation of Low-Pass Multibit Delta-Sigma Modulators', Master Thesis, Department of Electrical Engineering, National Taiwan University Taipei, Taiwan, June, 2001. [26] D. B. Ribner, R. D. Baertsch, S. L. Garverick, D. T. McGrath, J. E. Krisciunas and T. Fujii, 'A Third-Order Multistage Sigma-Delta Modulator with Reduced Sensitivity to Nonidealities,' IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1764-1773, December 1991. [27] R. J. Baker, H. W. Li and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation, John Wiley & Sons, New York, 1998. [28] Yin, G.M. Eynde, F.O. Sansen, 'W.A, High-Speed CMOS Co mparator with 8-B Resolution,' IEEE J. Solid-State Circuits, vol. 27, no. 2, Feb 1992. [29] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, 'Fat Tree Encoder Design for Ultra-High Speed Flash A/D Converters,' IEEE 45th Midwest Sym. Circuits and Systems, vol. 2, pp. 87-90, 2002. [30] C. A. Chao, 'Design and Implementation of High Input Bandwidth Sigma-Delta Modulator,' Master Thesis, Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan, June, 2003. [31] R. Baird and T. Fiez, 'Linearity Enhancement of Multibit Σ∆ A/D and D/A 88 Converters Using Data Weighted Averaging,' IEEE Trans. Circuits and Systems II, vol. 42, no.12, pp. 753-762, December 1995. [32] O. Nys and R. K. Henderson, 'A 19-Bit Low-Power Multibit Sigma-Delta ADC Based on Data Weighted Averaging,' IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 933-942, July 1997. [33] A. Yasuda, H. Tanimoto, and T. Iida, 'A Third-order SD Modulators Using second-Order Noise-Shaping Dynamic Element Matching,' IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1879-1886, December 1998. [34] S. Brigat , F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, and F. Maloberti, 'Modeling Sigma-Delta Modulator Non-Idealities in SIMULINK(R),' IEEE Int. Sym. on Circuits and Systems, vol. 2, pp.384 – 387, 30 May-2 June, 1999. [35] R. Schreier, G. C. Temes, Understanding Delta-Sigma Data Converters, John Wiley & Sons, 2005. [36] J. H., Guo, 'The Design and Implementation of Low Voltage CMOS Delta Sigma Modulators,' Ph.D. Thesis, Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, June, 2003. [37] Y. C. Yen, 'Design and Implementation of Multibit Sigma Delta D/A,' Master Thesis, Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan, June, 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35770 | - |
| dc.description.abstract | 在這篇論文中，我們設計並以交換電容電路實現了一個多位元的三角積分調變器。在多位元的調變器中存在一個提供回授信號的數位類比轉換器，由於該數位類比資料轉換器是由多個單位電容所構成，這些單位電容很容易因為積體電路製程或是電路的實體佈局時產生元件不匹配的效應，此一不匹配效應所帶來的非線性失真將直接由調變器輸出，而無法經由三角積分調變器本身的雜訊整形技術獲得任何的改善。為了改善這個問題，本調變器應用了動態元件匹配(Dynamic Element Matching)技術來降低不匹配誤差。其中，資料加權平均(DWA)演算法因與其他的動態元件匹配演算法相較，具有一階雜訊整形特性，能快速降低誤差與電路易於實現的優點，所以被我們採用於設計的調變器中。
設計的調變器信號頻寬為24kHz，可以應用於音頻的領域上。整個調變器是以混合訊號模式進行設計，並以Matlab進行調變器的建模與行為模擬。最後我們以TSMC 0.18um 1P6M 3.3V製程，利用Hspice與Spectre軟體進行電路的設計、模擬驗證與佈局。 | zh_TW |
| dc.description.abstract | In this Thesis, we designed and implemented an oversampling multi-bit delta-sigma modulator. Multi-bit delta-sigma modulator uses an internal DAC to provide the feedback signal. However, elements mismatch in DAC due to process variation will results in non-linear distortion and cannot be noise shaped by the delta-sigma modulation loop, this will degrade the performance of a delta-sigma modulator very much.
In order to reduce the mismatch error of DAC, many dynamic element matching (DEM) algorithms have been proposed. Compared with other algorithms, the data weighting averaging (DWA) technique is used in our design due to it has the advantage of fast error cancellation and easy circuit implementation. We use TSMC 0.18um 1P6M process and mixed-signal design methodology for our work. The designed modulator presents a 24 kHz signal bandwidth and can be used in audio application. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:09:15Z (GMT). No. of bitstreams: 1 ntu-94-P92943008-1.pdf: 1283555 bytes, checksum: 557fce8809f7e6f6aba750fc47c28892 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | ABSTRACT ................................................................................................................I
TABLE OF CONTENTS.................................................................................................. III LIST OF FIGURES .........................................................................................................VII LIST OF TABLES ............................................................................................................ XI CHAPTER 1 INTRODUCTION ................................................................................ 1 CHAPTER 2 DELTA-SIGMA MODULATOR FUNDAMENTALS......................... 3 2.1 Quantization and Quantization Noise ........................................................... 4 2.2 Oversampling Techique ................................................................................ 8 2.3 Delta-Sigma Modulators............................................................................. 10 2.3.1 First-Order Delta-Sigma Modulator .................................................... 10 2.3.2 Second-Order Lowpass Delta-Sigma Modulators ............................... 17 2.3.3 Bandpass delta-sigma Modulators ....................................................... 19 2.4 The Third and High-Order Delta-Sigma Modulators ................................. 21 2.4.1 Single-Loop High-Order Delta-Sigma Modulators ............................. 21 2.4.2 Multi-Stage Noise Shaping Single-Loop Delta-Sigma Modulators .... 23 CHAPTER 3 DESIGN OF MULTIBIT DELTA-SIGMA MODULATORS ............ 25 3.1 Linearity Issues of Multibit of Multibit Delta-Sigma Modulators.............. 26 3.2 Multi-bit Noise-Shaping and Dynamic Element Matching ........................ 29 3.2.1 Dynamic Element Random Averaging................................................. 31 3.2.2 Conventional Clocked Averaging ........................................................ 33 3.2.3 Individual Level Averaging.................................................................. 35 3.2.4 Data Weighted Averaging ........................................................................ 36 CHAPTER 4 SYSTEM AND CIRCUIT SPECIFICATIONS.................................. 41 4.1 System Architectures and Specifications.................................................... 41 4.1.1 Noise Design........................................................................................ 43 4.1.2 Dynamic-Range Scaling ...................................................................... 46 4.2 Thermal Noise and Capacitor Sizing .......................................................... 48 4.3 OP Amplifier Specification......................................................................... 50 4.3.1 Slew Current ........................................................................................ 51 4.3.2 Linear Settling Time and Unit Gain Frequency................................... 51 4.3.3 Transconductance Specification .......................................................... 54 4.3.4 DC Gain of Op Amp ............................................................................ 55 4.4 MATLAB Behavior Modeling and Simulation........................................... 55 CHAPTER 5 CIRUIT DESIGN AND IMPLEMENTATION.................................. 59 5.1 Integrator..................................................................................................... 59 5.2 Operational Amplifier ................................................................................. 61 5.2.1 Folded-Cascode Amplifier................................................................... 62 5.2.2 Common-Mode Feedbacks .................................................................. 66 5.2.3 Bias Circuit for the Operational Amplifier .......................................... 68 5.3 Four-Bit Quantizer ...................................................................................... 71 5.3.1 Switched-Capacitor Comparator.......................................................... 73 5.3.2 Comparator .......................................................................................... 73 5.3.3 Fat Tree Thermometer-to-Binary Encoder........................................... 76 5.3.4 Simulation Result of Quantizer............................................................ 77 5.4 Clock Genterator......................................................................................... 78 5.5 DWA Control Unit ...................................................................................... 79 5.6 Whole System Simulation........................................................................... 81 CHAPTER 6 CONCLUSION................................................................................... 83 REFERENCE .............................................................................................................85 | |
| dc.language.iso | en | |
| dc.title | 超取樣三角積分調變器的設計與製作 | zh_TW |
| dc.title | Design and Implementation of an Oversampling Delta-Sigma Modulator | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),林宗賢(Tsung-Hsien Lin),李泰成(Tai-Cheng Lee) | |
| dc.subject.keyword | 三角積分調變器,動態元件匹配,資料加權平均, | zh_TW |
| dc.subject.keyword | Delta-Sigma Modulator,DEM,DWA, | en |
| dc.relation.page | 88 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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