請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35560
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Ming-Home Tasi | en |
dc.contributor.author | 蔡明宏 | zh_TW |
dc.date.accessioned | 2021-06-13T06:58:29Z | - |
dc.date.available | 2005-08-01 | |
dc.date.copyright | 2005-08-01 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-27 | |
dc.identifier.citation | [1] P. Gray and R. Meyer, “Future directions in silicon ICs for RF personal communications,” IEEE Custom IC conference, pp. 83-90, 1995.
[2] S. Heinen, S. Beyer, and J. Fenk, “A 3.0V 2 GHz transmitter IC for digital radio communication with integrated VCOs,” Proceedings of IEEE International Solid-State Circuits Conference, pp. 150-1, Feb. 1995. [3] T. Riley, M. Copeland, “A simplified continuous phase modulator technique,” IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, vol. 41, no. 5, pp. 321-328, May 1994. [4] B. Razavi, “Monolithic Phase-Locked Loops and Clock Recovery Circuits,” IEEE PRESS, 1996. [5] V. F. Kroupa, “Jitter and Phase Noise in Frequency Dividers,” IEEE Trans. on Instrumentation and Measurement, vol. 50, no. 5, pp. 1241-1243, Oct. 2001. [6] P.M. Aziz, H. V. Sorensen, J. vn der Spiegel, “An overview of sigma-delta converters,” IEEE Signal Processing Magazine, vol. 13, pp. 61-84, Jan. 1996. [7] J. Craninckx and M. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996. [8] M. Perrot, “Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers,” PhD Thesis, Sep. 1997. [9] Michael H. Perrot, “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5Mb/s GFSK Modulation,” IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec. 1997. [10] Pietro Andreani and Sven Mattisson, “On the Use of MOS Varactors in RF VCO’s,” IEEE J. Solid-State, vol.35, no.6, pp. 905-910, June 2000. [11] B. Razavi, “Design of Analog CMOS Integrated Circuits,” International Edition, 2001. [12] B. Razavi, “RF Microelectronics,” Prentice Hall, Inc, 1998. [13] Emad Hegazi, and Asad A. Abidi, “A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-m CMOS,” IEEE J. Solid-State Circuits,” vol. 38, pp. 782-792, May 2003. [14] S. Cicero, and Zhenhua Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 1039-1045, July 2000. [15] Lu Jianhua, and Wang Zhigong, “Design Techniques of CMOS SCL circuits for Gb/s Applications,” ASIC, 2001. Proceedings. 4th International Conference, pp. 559 -562, OCT. 2001. [16] B. Miller, and B. Conley, “A Multiple Modulator Fractional-N Divider,” in Proc. 44th Annu. Symp. Frequency Control, May 1990, pp. 559-567. [17] Taizo Yamawaki, “A 2.7-V GSM RF Transceiver IC,” IEEE J. Solid-State Circuits, vol. 32, pp. 2089-2096, Dec. 1997. [18] M. Kozak, I. Kale, and T. Bourdi, “A pipelined all-digital delta-sigma modulator for fractional-N frequency synthesis,” IMTC 2000. Proceedings of the 17th IEEE, Vol. 2, pp. 1153-1157, May 2000. [19] Sudhakar Pamarti, and Ian Galton, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-Mb/s In-Loop Modulation,” IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, Jan. 2004. [20] P. Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, pp. 744-748, May 1996. [21] T. A. D. Riley, “Delta-sigma Modulation in Fractional-N Synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993. [22] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” in Proc. ISCAS’99, 1999, pp. 545-548. [23] Michael H. Perrott, “A Modeling Approach for S–D Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002. [24] S. Cicero, and Zhenhua Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 1039-1045, July 2000. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35560 | - |
dc.description.abstract | 在GSM手機通訊標準中,調變信號的方式是GMSK。它是一種連續相位的調變方式,為GFSK的一種。在本論文的研究中,建立了一套使用Simulink的相位調變器行為模型來探討他頻率及spectrum。在晶片中使用一個三角積分調變除小數頻率合成器來實現部分相位調變器的射頻電路。其中相位頻率比較器、電流泵、多模數除頻器及壓控震盪器是用0.35μm混和信號 2P4M CMOS製程的積體電路實現,而三角積分調變器是由 MATLab 通過 pattern generator 來實現。 | zh_TW |
dc.description.abstract | In GSM communication system, the modulation of the modulated signals are GMSK. It is a kind of modulation way of continuiing phase, a kind of GFSK modulation way. In this work, we set up a complete behavior model of phase modulator in Simulink environment. In this chip, we use a sigma-delta fractional-N frequency synthesizer to implement partial RF circuit of the phase modulator. A phase frequency detector, a charge pump ,a multi-modulus divider and a voltage-controlled oscillator are fabricated with 0.35μm 2P4M CMOS technology and are operated over 1.8 GHz. The sigma-delta modulator is implemented by Simu-link and the pattern generator. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T06:58:29Z (GMT). No. of bitstreams: 1 ntu-94-R91943048-1.pdf: 8292119 bytes, checksum: 2c969cadd52dc1682870252760c9b00b (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Table of Contents
Table of Contents I List of Figures V List of Tables XI Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Basic Concepts and System Overview 3 2.1 Modulators 3 2.1.1 Areas of Focus 3 2.1.2 Modulator Architectures 4 2.2 Phase-locked Loops 6 2.2.1 Basic Topology 6 2.2.2 PLL’s Linear Models 8 2.2.3 PLL’s Basic Components 13 2.2.4 Noise in the PLL 16 2.3 Frequency Synthesizers 20 2.3.1 Frequency Multiplication and Integer-N Frequency Synthesizers 20 2.3.2 Fractional-N PLL 22 2.4 Sigma-Delta Modulation on Fractional-N PLL 26 2.4.1 Quantization Noise of Sigma-Delta Modulators 28 2.4.2 High Order Sigma-Delta Modulators 29 2.4.3 Multi-Stage Noise Shaped (MASH) Structure 30 Chapter 3 Gaussian Minimum Shift Keying Background and GMSK Modulators 33 3.1 Frequency Plan 33 3.2 Modulation Format 35 3.2.1 MSK Modulation 35 3.2.2 Gaussian MSK (GMSK) 37 3.3 The Challenge of Achieving High Data Rates and Low Noise 41 Chapter 4 Behavioral Models of Sigma-Delta Fractional-N PLL 47 4.1 Integer-N and Fractional-N PLL Behavior Simulations 47 4.1.1 Integer-N PLL 48 4.1.2 Fractional-N PLL 49 4.2 Simulations of Fractional-N Modulated by Sigma-Delta GMSK 51 4.2.1 Sigma-Delta Simulations 51 4.2.2 GMSK Simulations 54 4.2.3 Sigma-Delta GMSK Fractional-N PLL 55 Chapter 5 Circuit Implementation of Building Blocks and Components 61 5.1 Phase Frequency Detector 61 5.2 Charge Pump 63 5.3 Low-Pass Filter 64 5.4 Voltage-Controlled Oscillator 67 5.4.1 MOS Varactors 67 5.4.2 Inversion-Mode MOS Varactors 68 5.4.3 Voltage-Controlled Oscillator Design 69 5.5 Programmable Dividers 70 5.5.1 Architecture Approaches 70 5.5.2 Type-I of the Prescalers 73 5.5.3 Type-II of the Prescalers 79 Chapter 6 Simulation Results 83 6.1 The Circuit Pre-Simulations of the PLL 83 6.1.1 The Pre-Simulations of PFD and CP 83 6.1.2 The Pre-Simulations of the Voltage-Controlled Oscillator 85 6.1.3 The Pre-Simulations of the Prescalers 87 6.2 The Circuit Post-Simulations of the PLL 88 6.2.1 The Post-Simulations of PFD and CP 88 6.2.2 The Post-Simulations of the Voltage-Controlled Oscillator 90 6.2.3 The Post-Simulations of the Prescalers 91 6.2.4 The Post-Simulations of the Close Loop 92 Chapter 7 Measure Results and Conclusions 95 7.1 Measure Results and Discussion 95 7.1.1 Testing Setup 95 7.1.2 Chip Measurement 96 7.1.3 Discussion of the Chips 98 7.2 Conclusions 99 7.3 Appendix 99 7.3.1 The Ratiocination of the Chip Measurement Results 99 7.3.2 The Optimum of the Design Issues 100 7.3.3 The Comparisons between fractional-N PLL and integer-N PLL 106 7.3.4 The Working Mode of the PMOS Varactor 108 7.3.5 The Working Mode of the Charge Pump Circuit 109 Bibliography 111 | |
dc.language.iso | en | |
dc.title | 應用小數頻率合成器於GMSK調變 | zh_TW |
dc.title | A GMSK Modulator by Using a Fractional-N Frequency Synthesizer | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),柏振球(Jenn-Chyou Bor) | |
dc.subject.keyword | 頻率合成器,鎖相迴路,調變, | zh_TW |
dc.subject.keyword | PLL,Fractional-N,GMSK modulator, | en |
dc.relation.page | 112 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-94-1.pdf 目前未授權公開取用 | 8.1 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。