請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35191
標題: | Dynamically Reconfigurable Hardware Library based of FPGA |
作者: | Chien-Wei Ho 何建緯 |
指導教授: | 顧孟愷 |
關鍵字: | 現場可重定址陣列,系統晶片,矽智財, FPGA,SOC,IP, |
出版年 : | 2005 |
學位: | 碩士 |
摘要: | Nowadays when we want to do a design, we need to software-hardware partition first. It is because that we want to put some heavy loading parts of the design into hardware. That would improve the performance of the whole design. Generally if we can put as many functions into hardware as we can, we will get much performance improvement. So, besides the software-hardware partitioning consideration, we need to have a rapidly method to let the Compute Intensive Part (CIP) run in hardware. We propose a Dynamically Reconfigurable Hardware Library (DRHL) method. When we put the CIP into DRHL, we can change to use software Intellectual Property (IP) or hardware IP smoothly. So, we can easily test if our software IP and hardware IP have the same functionality. We also can enhance computation power in System-On-Chip (SOC) with FPGA blocks. Our method provides to reach a better trade-off among flexibility performance and power. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35191 |
全文授權: | 有償授權 |
顯示於系所單位: | 資訊工程學系 |
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ntu-94-1.pdf 目前未授權公開取用 | 706.25 kB | Adobe PDF |
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