可自動化產生的匯流排包裝器方法論

Abstract

由於產品上市時間的壓力和晶片複雜度的成長，近來的設計工具和方法對於研發百萬邏輯閘的單晶片系統是不合適的。如果我們想更快的研發晶片系統設計，一個可靠的計畫去重複的使用矽智財是一個重要的問題，而晶片上的溝通對於這個問題是一個主要的解決方法。在這個論文中，我提出一個新的方法去設計匯流排包裝器介面且自動化產生。因為這個匯流排包裝器可以在不同的協定下轉換介面，它不只可以達到矽智財的重覆利用且減少當新的矽智財加入單晶片平台元件所需的複雜度。在我們的方法論中，我們選擇了擁有AHB匯流排系統的FPGA板作為實驗平台並且在這個平台上連接我們的匯流排包裝器和各種不同的IP當作個案研究。最後，為了減少硬體的代價和設計者的所花費的努力，我發展一個程式去自動化產生這個匯流排包裝器。使用者只要輸入一些必需的矽智財資訊像協定形態，頻寬…等，這個程式就可以對於各個應用程式產生完美合適的匯流排包裝器。

As time-to-market pressures and chip complexities growing, current design tools and methodologies are inadequate for developing million gates System-On-Chip (SOC). If we intend to develop SOC designs more quickly, a reliable scheme to reuse Intellectual Properties (IP) cores is the important issue, and on-chip communication is considered a key technology for this. In this thesis, I propose a new methodology to design the bus wrapper interface and generate it automatically. Because the bus wrapper is able to transfer the interface between different protocols, it can not only achieve the goal of IP reuse but also reduce the complexity when a new IP component intends to connect SOC platforms. In our methodology, we choose the Field Programmable Gate Array (FPGA) board which has Advanced High Performance (AHB) bus system as the experiment platform and connect our bus wrapper with the different IP cores on the board as the case study. Finally, in order to reduce hardware overhead and designers’ efforts, I develop a program to generate the wrapper interface automatically. This program can produce a suitable perfect wrapper interface for each application by entering some parameters which contain the necessary information of IP cores such as protocol type, bit width and data dependant or not.