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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Feipei Lai) | |
| dc.contributor.author | Kun-Lin Tsai | en |
| dc.contributor.author | 蔡坤霖 | zh_TW |
| dc.date.accessioned | 2021-06-13T06:03:59Z | - |
| dc.date.available | 2006-07-03 | |
| dc.date.copyright | 2006-07-03 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-06-19 | |
| dc.identifier.citation | [1] U.S. Environmental Protection Agency (EPA) http://epa.gov/
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Vecchi, “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671—680, 1983. [66] F. Romeo and A. Sangiovanni-Vincentelli, “Probabilistic Hill Climbing Algorithms: properties and Applications,” Proc. of the 1985 Chapel Hill Conference on VLSI, pp. 393—417, 1985. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/34343 | - |
| dc.description.abstract | 可攜式消費電子市場經常需要較強大功能、較小、較輕及較長電池壽命的產品。在以電池為主要供電來源的手持式系統中，低耗電的設計需求遽速上升，主要的原因是降低能量消耗能夠讓此類設備使用時間延長。既便是在高階電腦系統中，低功率仍是一個重要的設計考量，因為昂貴的冷卻、包裝成本以及低可靠度常與大量功率消耗有關。
高階合成(high-level synthesis)包含排程(scheduling)、連結(binding)、與分配(allocation)，在本論文中，我們主要著重於多重電壓排程方法，因為多重電壓技術在低功率設計領域中是一項相當有用的方法。多重電壓排程指的是配置一個合適的電壓給控制資料流程圖(CDFG)中的每個節點，以便於整個系統在給定的時間限制下，降低其功率消耗。在本篇論文中，我們提出了兩個多電壓排程方法：多重供應電壓(multiple supply voltage)排程以及雙供應電壓雙臨界電壓(dual supply voltage and dual threshold voltage)排程。不同於以往的研究總是將焦點集中在臨界路徑上，並利用鬆弛時間(slack time)來調整其他非臨界節點的電壓，使用本論文所提出的方法能夠處理所有的節點而不需考慮臨界路徑的問題，優點是可以讓電壓配置更具有彈性。在多重供應電壓排程中，我們分析並比較多重電壓對高階合成的影響，而在雙供應電壓雙臨界電壓排程中，我們不但考慮動態功率消耗，也同時將靜態功率消耗列入考量。此外，我們也提出了一個結合基因演算法與模擬退火法的特殊演算法來解決高階雙電壓排程問題。 | zh_TW |
| dc.description.abstract | The portable consumer electronics market is constantly demanding more powerful capabilities, smaller and lighter products, and longer battery life. Demand has risen sharply for low power consumption in battery-powered hand-held systems owing to the key requirement to reduce power dissipation to extend service. Even in high-end computer systems, low power is still a critical design consideration, since the expensive cooling and packaging costs and lower reliability associated with high-level on-chip power dissipation are significant.
High-level synthesis consists of scheduling, binding and allocation, and in this dissertation the main focus falls on the multiple voltages scheduling aspect. The multiple voltage technique is one of several useful techniques in the low power design field. The multiple voltage scheduling refers to the assignment of a voltage level to each operational node in a data flow graph to minimize the total power consumption within a given computation time. In this dissertation, we propose two multiple voltage scheduling methods: multiple supply voltage (MSV) scheduling and dual supply voltage and dual threshold voltage (DSDT) scheduling. Unlike previous research, which focused on the operational nodes in the critical path and used the slack time to change the voltage of other nodes, our methods deal with all nodes without considering whether a node is in the critical path, our method deals with all nodes without considering whether a node is in the critical path. The advantage of this method is that the voltage assignment becomes very flexible. In the MSV scheduling, we analyze and compare the multiple voltage effect on high-level synthesis, and in DSDT scheduling, we take into account not only the dynamic power but also the static power consumption. Besides, a special algorithm which combines genetic algorithm and simulated annealing algorithm is proposed to solve the high-level dual-voltage scheduling problem. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T06:03:59Z (GMT). No. of bitstreams: 1 ntu-95-D90921005-1.pdf: 664079 bytes, checksum: 18eee830eed7951cfad4fe97f7bbef90 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Chapter 1 Introduction..................................1
1.1 Low Power Requirement..........................1 1.2 Design Abstraction and Synthesis...............2 1.2.1 Low Power Synthesis............................5 1.3 Source of Power Dissipation....................7 1.3.1 Dynamic Power..................................7 1.3.2 Short-circuit Power............................8 1.3.3 Leakage Power..................................9 1.3.4 Static Power..................................10 1.4 Motivation....................................10 Chapter 2 Preliminary and Related work.................15 2.1 High-level Synthesis..........................15 2.2 High-level Synthesis Flow.....................17 2.3 High-level Description........................20 2.4 High-level Synthesis Problem..................23 2.4.1 Scheduling Problem............................24 2.5 The Simple ASAP Scheduling Algorithm..........25 2.6 Multiple Voltage Scheduling...................27 Chapter 3 Multiple Supply Voltage (MSV) Scheduling.....31 3.1 MSV Scheduling Problem Description............31 3.2 Simulated Annealing Algorithm.................34 3.3 MSV Scheduling Flow...........................37 3.4 Two Phases Scheduling Algorithm...............38 3.4.1 1st-level Scheduling..........................38 3.4.2 2nd-level Adjusting.......................... 41 3.4.3 An Example....................................43 3.5 Experimental Results of MSV Scheduling........45 3.5.1 Experimental Environment and Cell Library.....45 3.5.2 Results and Discussions.......................46 3.6 Summary.......................................51 Chapter 4 Dual Supply Voltage and Dual Threshold Voltage (DSDT) Scheduling......................................53 4.1 DSDT Scheduling Problem.......................53 4.2 Genetic Algorithm based Simulated Annealing Scheduling Algorithm...................................55 4.3 DSDT Scheduling Flow..........................57 4.4 DSDT Scheduling Algorithm.....................60 4.4.1 Individual and Chromosome Representation......60 4.4.2 GASA Operations and Parameters................61 4.4.3 GASA Algorithm................................65 4.4.4 An Example....................................66 4.5 Experimental Results..........................68 4.5.1 Experimental Environment and Cell Library.....68 4.5.2 Results and Discussions.......................69 4.6 Summary.......................................72 Chapter 5 Allocation and Binding.......................75 5.1 Allocation....................................75 5.1.1 Resource Allocation...........................75 5.1.2 Register Allocation...........................76 5.2 Binding.......................................79 5.3 Simultaneous Allocation and Binding...........82 5.3.1 Conflict Graph Construction...................82 5.3.2 Most Expensive First Binding Algorithm........83 Chapter 6 Conclusions..................................87 6.1 Summary of Contribution.......................87 6.2 Future Work...................................89 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 高階合成 | zh_TW |
| dc.subject | 多重電壓 | zh_TW |
| dc.subject | 排程 | zh_TW |
| dc.subject | high-level synthesis | en |
| dc.subject | multiple voltage | en |
| dc.subject | scheduling | en |
| dc.subject | low power | en |
| dc.title | 使用多重電壓之低功率高階合成方法 | zh_TW |
| dc.title | Low Power High-Level Synthesis Method using Multiple Voltages | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 莊仁輝,張延任,汪大暉,楊佳玲,顧孟愷,李鴻璋 | |
| dc.subject.keyword | 低功率,高階合成,多重電壓,排程, | zh_TW |
| dc.subject.keyword | low power,high-level synthesis,multiple voltage,scheduling, | en |
| dc.relation.page | 97 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-06-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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