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標題: | 利用類神經網路分析連通柱不連續結構之電氣特性與製程解空間 Electrical Characteristics of Via Discontinuity and Manufacturing Solution Space Analysis with the Neural Networks-Based Approach |
作者: | Ku-Teng Hsu 許顧騰 |
指導教授: | 黃天偉(Tian-Wei Huang) |
關鍵字: | 類神經網路,連通柱,不連續結構,阻抗匹配,製程解空間, neural network,via,discontinuity,matching impedance,design solution space, |
出版年 : | 2006 |
學位: | 碩士 |
摘要: | 當資料傳輸速率到達數個十億位元的範圍以上,在印刷電路板上由連通柱所造成的不連續效應將不能再被忽略。為了分析連通柱結構對於信號完整度上的影響,通常會先針對實際的結構尺寸建立集總模型。連通柱的π等效電路包含了一個串接電感和兩個並接電容。利用全波模擬軟體可以計算出電容和電感值。全波模擬軟體雖然可以得到非常準確的結果,然而,卻需要花費相當多的時間,無法有效率地應用在實際的電路設計上。
近年來,利用電磁場觀念訓練的類神經網路分析方法逐漸被重視。利用電磁模擬軟體得到的數據,可以訓練出精確且計算迅速的類神經模型。利用這些類神經模型可以加快電路設計的時程,同時保有電磁模擬軟體的準確性。本論文提出一種方法,可以用來設計低反射雜訊的被動元件,如連通柱或是相似結構等。訓練完成後的多層類神經網路,可以針對特定的結構尺寸,快速計算出結構的阻抗值。當類神經網路模型建立之後,可以很輕易的在有興趣的尺寸範圍內,求出所有結構的阻抗值,並且找出和前後端微帶線阻抗匹配的連通柱設計解空間。最後利用時域模擬軟體與量測結果,來驗證解空間的正確性。 As the data rates increase into the multi-gigabit range, the effect of via discontinuities on printed circuit board becomes non-negligible. Lumped-circuit models for via structures are usually constructed from their geometries to understand the signal integrity issues. The π-type equivalent circuit of a via consists of two excess capacitances and an excess inductance. Capacitance and inductance values can be computed using a full-wave solver. Full-wave characterization can lead to accurate results, however, it takes the tremendous computational efforts and is not practical for an efficient circuit design. In recent years, the electromagnetically trained artificial neural network (EM-ANN) approaches have gained the recognition. Accurate and fast neural models can be developed from the simulated EM data. These neural models can speed up the circuit design with the accuracy compared to that of a full-wave solver. This thesis describes a methodology for designing a low-reflection passive component such as via structures or similar structures. The multi-layer neural network is trained to fast predict the impedance of vias based on the physical dimensions. Once the EM-ANN model has been trained, it is easy to derive a whole of impedance profile over the desired physical dimension range. The via structures are chosen with reference to the design solution space by the matching impedance thus to the microstrip line from two interconnected sides. The solution space is demonstrated by the time-domain simulations and measurements, accordingly. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33891 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
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