請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33727
標題: | 全域穩定之CMOS低壓降線性穩壓器 A CMOS Low Dropout Voltage Regulator with Full-Range Stability |
作者: | Chun-Hsiang Huang 黃俊翔 |
指導教授: | 陳秋麟 |
關鍵字: | 低壓降,穩壓器,全域穩定, CMOS,LDO,Regulator,Stability, |
出版年 : | 2006 |
學位: | 碩士 |
摘要: | 穩定度一直是在設計低壓降線性穩壓器的過程中一個重要的議題。在傳統的電路架構中,負載電流大小以及輸出電容值為兩項主要影響穩定度的因素。因此,到目前為止已有許多補償的方法被提出來改善整體的效能。就應用的方面來說大致分為輸出電容外接和內建兩類,利用電容外接的方式可增加輸出電容的容值並產生一個主極點維持穩定,主要應用在系統較大對於面積較不注重的產品如電視。另一類的低壓降線性穩壓器的輸出電容靠著米勒效應使得電容值小且可整合在晶片當中,省下不少面積因此適合應用在可攜式電子產品裡作為穩定的直流電壓源。
綜觀這兩類的低壓降線性穩壓器,對於輸出電容都有特定範圍的限制。因此,本論文提出一個對任意的輸出電容值皆穩定的低壓降線性穩壓器,利用類似米勒效應的電容放大和並聯的功率電晶體架構兩種技巧產生一連串的極點和零點使得控制迴路在單一增益頻率之前都能有足夠的相位來保持穩定。整個電壓穩壓器採用0.18μm、1P6M的CMOS製程。佈局後的模擬結果應證了理論的分析,顯示無論電容大或小,整個系統皆能穩定且直流增益有50dB,最大可提供的輸出電流為100mA。 Stability is the important issue during designing the LDO linear regulators. In the conventional architecture, the key factors affecting the stability are the variation of load current and the value of output capacitor. Therefore, there have been many proposed compensation methods to improve whole performance. According to the applications and output capacitor, the LDO linear regulators can be approximately classified into two groups: off-chip and on-chip output capacitor. These LDO linear regulators with off-chip capacitor have larger capacitance at output node and generate the dominant pole at low frequencies to achieve the stability. They are mostly used for the products with bigger system and area like TV. The other LDO linear regulators have smaller output capacitor, and thus the capacitor can be integrated into the chip, saving the total chip area. For the reason this kind of LDO linear regulators are well suited as a stable dc voltage supply for portable electronic devices. This thesis proposes a LDO linear regulator stable for any output capacitor. By utilizing two techniques: capacitor multiplier and parallel power transistors a series pole-zero pairs are generated at frequencies to make the control loop has enough phase. The regulator is designed in a 0.18 μm 1P6M CMOS process. The post-layout simulation results verify the theoretical analysis and show that the regulator can be stable with any load capacitor. Besides, the DC gain is around 50 dB, and the maximum load current is 100mA. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33727 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-95-1.pdf 目前未授權公開取用 | 1 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。