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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
| dc.contributor.author | Tsui-Yee Ling | en |
| dc.contributor.author | 林翠薏 | zh_TW |
| dc.date.accessioned | 2021-06-13T05:44:19Z | - |
| dc.date.available | 2006-07-17 | |
| dc.date.copyright | 2006-07-17 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-14 | |
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Blaauw, ¿AU: Timing Analysis Under Uncertainty,' In Proceeding of International Conference on Computer-Aided Design, page 615-620, November 2003. [7] J. R. Black, Electromigration-a Brief Survey and Some Recent Results, IEEE Transaction on Electron Devices, page 338-347, 1969. [8] S. Boyd and L. Vandenberghe, Convex Optimization, Cambridge, 2004. [9] C.Chatfield, Introduction on Multivariate Analysis, Chapman and Hall, 1980. [10] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Public, 1995. [11] H. Chang and S. S. Sapatnekar, Statistical Timing Analysis Considering Spacial Correlations using A Single Pert-Like Traversal,' In Proceeding of International Conference on Computer-Aided Design, page 621-625, November 2003. [12] J. Chern, J. Huang, L. Arledge, P. Li, and P. Yang, Multilevel Metal Capacitance Models for CAD Design Synthesis Systems,' IEEE Electron Devices Letters, page 32-34, January 1992. [13] C.-P. Chen, Y.-W. Chang, and D. F. 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L, Rivest, Introduction to Algorithms, The MIT Press, 1990. [19] W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wide Band Ampli‾ers,' J. Applied Physics, volume 19, number 1, 1948. [20] B. Goplen and S. Sapatnekar, Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach,' In Proceeding of International Conference on Computer-Aided Design, page 86-89, November 2003. [21] H.-R. Jiang, J.-Y. Jou ,and Y.-W. Chang, Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing based on Lagrangian Relaxation,' In Proceeding of Design Automation Conference, page 90-95, June 1999. [22] H.-R. Jiang, Y.-W. Chang, and J. Y. Jou, Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing,' IEEE Transactions on Computer-Aided Design, volume 19, page 999-1010, September 2000. [23] V. Khandelwal, A. Davoodi, and A. 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Samaan, The Impact of Device Parameter Variation on the Frequency and Performance of VLSI Chips,' In Proceeding of International Conference on Computer-Aided Design, page 343-346, September 2004. [34] Semiconductor Industry Association, International Technology Roadmap for Semiconductors 1999 Edition, November 1999. [35] A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power, Michigan, 2005. [36] C.-H. Tsai and S.-M. Kang, Cell-Level Placement for Improving Substrate Thermal Distribution,' IEEE Transactions on Computer-Aided Design, volume 19, page 253-266, February 2000. [37] C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, First-Order Incremental Block-Based Statistical Timing Analysis,' In Proceeding of Design Automation Conference, page 331-336, June 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33662 | - |
| dc.description.abstract | 製程變異已成為奈米電路設計的可信度與連線延遲的嚴峻考驗。此外，極劇上升的功耗值與電路合成密度將導致極高的操作環境溫度。溫度，如同電致遷移與電壓，將會嚴重影響到連線的延遲與可信度。考慮製程變異，我們提出了第一個利用統計分析的方法，在符合時序與熱效應良率的條件下，使用邏輯閘與佈線形狀調整技術，最佳化電路的總面積。我們將問題轉換成二次圓錐規劃，並且利用內點法快速解出答案。實驗結果顯示我們的統計方法能找到符合70.0%，84.1%，
99.9%良率條件限制的解答，並且平均上能分別減少44.03%，33.25%，21.74%電路總面積。除此之外，執行時間與電路大小的對數曲線顯示了，利用內點法來解二次圓錐規劃的問題可以得到一個接近線性的實際時間複雜O(N^0.9)， N代表電路大小。更值得一題的是，我們解二次圓錐規劃的時間複雜度比起過去研究提出的理論值O(N^1.3)還要來得更好。 | zh_TW |
| dc.description.abstract | Process Variation has become a crucial challenge on both interconnect delay and reliability of nanometer integrated circuit designs. Furthermore, the dramatic increase of ower consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM) and power, also significantly affects the delay and reliability of interconnects. Considering process variation, we present the firrst work to use statistical methods to optimize the circuit area under timing and thermal yield constraints by sizing both wires and gates. We model the problem as a second-order conic program (SOCP) and solve it with the interior-point optimization method. Experimental results show that our statistical algorithm can find solutions that satisfy all constraints and on average improves the circuit areas by respective 44.03%, 33.25%, and 21.74% with 70.0%, 84.1%, and
99.9% yields after wire and gate sizing. Further, the log-log curve of the runtime shows that our empirical time complexity is only about O(N^0.9) for solving SOCPs by the interior-point method, which is sublinear to the circuit size, N. In particular, our empirical time complexity is even better than the previously reported O(N^1.3) bound, showing our efficient implementation. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T05:44:19Z (GMT). No. of bitstreams: 1 ntu-95-R93921040-1.pdf: 491201 bytes, checksum: 7f170a151d7152d383076e86908cdc0d (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Abstract (Chinese) i
Abstract ii Acknowledgements iii List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1 Previous Works 2 1.2 Our Contributions 3 1.3 Organization of the Thesis 5 Chapter 2. Preliminaries 6 2.1 Second-Order Conic Programming (SOCP) 6 2.2 Thermal Model 8 2.3 Variation Model of Performance Parameters 10 2.3.1 Variability of the Physical Parameters considering Correlations 10 2.3.2 Variations of Performance Parameters 12 Chapter 3. Deterministic Interconnect Optimization 14 3.1 Problem Description 14 3.1.1 Influence of Self-Heating on EM 14 3.1.2 Temperature-Dependent Delay 16 3.2 Deterministic Formulation of the Interconnect Optimization 16 3.2.1 EM Constraint 17 3.2.2 Timing Constraint 19 3.2.3 Power Constraint 21 3.2.4 Deterministic Problem Formulation 21 Chapter 4. Statistical Thermal-Driven Optimization Using SOCP 23 4.1 Statistical Problem Formulation 23 4.2 Parametric Yield Formulation using SOCP 25 4.3 Simultaneous Gate and Wire Sizing Optimization 29 4.4 Implementation 30 4.4.1 Data Structures 30 4.4.2 Time Complexity 30 Chapter 5. Experiment Results 36 Chapter 6. Conclusions and Future Work 45 6.1 Conclusions 45 6.2 Future Work 45 Bibliography 47 | |
| dc.language.iso | en | |
| dc.subject | 最佳化 | zh_TW |
| dc.subject | 熱效應 | zh_TW |
| dc.subject | 以統計分析 | zh_TW |
| dc.subject | 時序效能 | zh_TW |
| dc.subject | 電路 | zh_TW |
| dc.subject | Statistical | en |
| dc.subject | Optimization | en |
| dc.subject | Circuit | en |
| dc.subject | Timing | en |
| dc.subject | Thermal | en |
| dc.title | 以統計分析的熱效應與時序效能為限制之電路最佳化 | zh_TW |
| dc.title | Statistical Thermal- and Timing-Constrained Circuit Optimization | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林永隆(Youn-Long Lin),王廷基(Ting-Chi Wang),陳宏明(Hung-Ming Chen) | |
| dc.subject.keyword | 以統計分析,熱效應,時序效能,電路,最佳化, | zh_TW |
| dc.subject.keyword | Statistical,Thermal,Timing,Circuit,Optimization, | en |
| dc.relation.page | 51 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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