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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33656完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Ju-Yueh Lee | en |
| dc.contributor.author | 李儒岳 | zh_TW |
| dc.date.accessioned | 2021-06-13T05:44:15Z | - |
| dc.date.available | 2006-07-17 | |
| dc.date.copyright | 2006-07-17 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-17 | |
| dc.identifier.citation | [1] Paul Wielage and Kees Goossens, “Network on Silicon: Blessing or Nightmare?”, In Proc. of Euromicro Symposium on Digital System Design, pp. 196-200, Sept. 2002.
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De Micheli, “Guest Editors’ Introduction: The Network-on-Chip paradigm in Practice and Research”, IEEE Design & Test of Computers, Vol. 22, Issue 5, pp. 399-403, Sept 2005. [17] T.A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, R. Lauwereins, “Highly scalable network on chip for reconfigurable systems”, In Proc. of International Symposium on System-on-chip, pp. 79-82, Nov. 2003. [18] D. Bertozzi, A. Jalabert, Srinivasan Murali, R. Tamhankar, S. Stergiou, L. Benini, G. De Micheli, “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip”, IEEE Transactions on Parallel and Distributed Systems, Vol. 16, Issue 2, pp.113-129, Feb 2005. [19] Se-Joong Lee, Kangmin Lee, Seong-Jun Song, Hoi-Jun Yoo, “Packet-switched on-chip interconnection network for system-on-chip applications”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 52, Issue 6, pp. 308-312, June 2005. [20] Jian Liu, Li-Rong Zheng, H. Tenhunen, “A guaranteed-throughput switch for network-on-chip”, International Symposium on System-on-Chip, pp. 31-24, Nov. 2003. [21] E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander, “Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip”, In IEE Proc. of Computers and Digital Techniques, Vol. 150, Issue 5, pp. 294-302, Sept. 2003. [22] C.A. Zeferino, M.E. Kreutz, A.A. Susin, “RASoC: a router soft-core for networks-on-chip”, In Proc. of Design, Automation and Test in Europe Conference and Exhibition, Vol. 3, pp. 198-203, Feb. 2004. [23] C.A. Zeferino, A.A. Susin, “SoCIN: a parametric and scalable network-on-chip”, In Proc. of Symposium on Integrated Circuits and Systems Design, pp. 169-174, Sept. 2003. [24] C.A. Zeferino, F.G.M.E. Santo, A.A. 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Zafalon, “System level power modeling and simulation of high-end industrial network-on-chip”, In Proc. of Design, Automation and Test in Europe Conference and Exhibition, Vol. 3, pp. 318-323, Feb. 2004. [29] N. Genko, D. Atienza, G. De Micheli, J.M. Mendias, R.Hermida, F. Catthoor, “A complete network-on-chip emulation framework”, In Proc. of Design, Automation and Test in Europe, Vol. 1, pp. 246-251, 2005. [30] P.T. Wolkotte, G.J.M. Smit, M. Kavaldjiev, J.E. Becker, J. Becker, “Energy model of Networks-on-chip and a Bus”, In Proc. of International Symposium on System-on-chip, pp. 82-85, Nov. 2005. [31] G.M. Chiu, “The Odd-Even Turn Model for Adaptive Routing”, IEEE Transaction on Parallel and Distributed Systems, Vol. 11, Issue 7, pp. 729-738, July 2000. [32] P.T. Wolkotte, G..J.M. Smit, G.K. rauwerda, L.T. Smit, “An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip”, In Proc. of IEEE International Parallel and Distributed Processing Symposium, pp. 155a-155a, April 2005. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33656 | - |
| dc.description.abstract | 在先進的超大型積體電路設計當中，晶片系統(system-on-a-chip)是必然的趨勢。隨著製程不斷地縮小，晶片系統中各個IP之間的訊息交換變成是晶片設計上的一大挑戰，也是設計上最主要的考慮因素，為了克服這些訊息交換所造成的瓶頸，有許多研究提出以晶片網路(Network-on-chip, NoC)的方式提供可延伸並且可靠的晶片通訊方式。在晶片網路架構中，交換器(switch)是最重要的組成元件，所有晶片網路的特性以及其所提供的功能都必須藉由設計以及實現一個交換器架構來達成。在本篇論文中我們提出了一個在二維網格拓墣(2-D mesh topology)上的低功率交換器架構，利用減少緩衝器的(buffer)的使用個數以及調整大小，本篇研究可以有效的降低晶片網路的功率消耗，並且在此交換器架構當中，所提出的緩衝架構也有效的防止死結(deadlock)的發生。在本論文的實驗中，數據顯示和先前的交換器架構設計比較，我的交換器可使晶片網路架構降低約60%的功率消耗。 | zh_TW |
| dc.description.abstract | System-on-a-chip is a trend of modern circuit design. However, with the technology scales down, the inter-communication between IP cores becomes main challenge of SoC design. To overcome the communication problem, Network-on-Chip (NoC) is proposed to provide scalable and reliable on-chip communication. NoC switch (or so-called router) is the most important component of a NoC architecture, and all functions and properties of a NoC is carried out by designing and implementing a switch architecture. In this thesis, a low-power 2-buffer best-effort NoC switch architecture for 2D mesh NoC topology is proposed. By reducing the number of inside buffer and adjusting the buffer size, my work can effectively reduce NoC power consumption. Furthermore, the proposed architecture is free from deadlock since a novel buffering architecture is also proposed in this thesis. Experimental results show that the proposed architecture can save NoC switch power consumption up to 60% comparing with previous switch architecture. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T05:44:15Z (GMT). No. of bitstreams: 1 ntu-95-R93921041-1.pdf: 723503 bytes, checksum: b0a1b0cfc5c333cb3e01411e43b438cd (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | 1 Introduction 1
1.1 Low Power Requirement 1 1.2 Source of CMOS power dissipation 2 1.3 System-on-a-chip (SoC) 4 1.4 Network-on-chip (NoC) 5 1.5 Thesis organization 7 2 Background and Related Work 8 2.1 NoC architecture 8 2.2 Standardized communication protocol 11 2.3 Network protocol of NoC 12 2.4 NoC topology 14 2.5 Routing algorithm 19 2.6 Switch design 21 3 Proposed low power 2-buffer best-effort NoC switch design 24 3.1 Buffer power analysis in a NoC switch 25 3.2 Previous single FIFO NoC switch design and the deadlock problem 29 3.2.1 Previous design of single FIFO NoC switch 29 3.2.2 Deadlock in 2D mesh NoC 31 3.3 Low power 2-buffer best-effort NoC switch architecture 34 3.3.1 Packet format 34 3.3.2 Link communication protocol 35 3.3.3 2-buffer best-effort NoC switch architecture 37 4 Experimental Results 42 4.1 Experimental Environment 42 4.2 Experimental results 45 5 Conclusion 51 Bibliography 52 | |
| dc.language.iso | en | |
| dc.subject | 交換器架構 | zh_TW |
| dc.subject | 晶片系統 | zh_TW |
| dc.subject | 晶片網路 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | switch architecture | en |
| dc.subject | System-on-Chip | en |
| dc.subject | Network-on-Chip | en |
| dc.subject | Low Power | en |
| dc.title | 低功率晶片網路交換器架構設計 | zh_TW |
| dc.title | Low Power Network-on-Chip Switch Architecture Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張延任,楊佳玲,阮聖彰,顧孟愷 | |
| dc.subject.keyword | 低功率,晶片網路,晶片系統,交換器架構, | zh_TW |
| dc.subject.keyword | Low Power,Network-on-Chip,System-on-Chip,switch architecture, | en |
| dc.relation.page | 55 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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