利用預留元件及技術重新映射做工程修改命令的時序最佳化

Abstract

利用預留元件做重新繞線是一種在擺置階段後改變晶片功能或是修正晶片瑕疵的技巧。這個技巧過去一向由工程師手動執行，但是目前卻變的相當困難而不能再靠人力來完成。在這篇論文中，我們提出了一個兩階段的使用預留元件修正晶片瑕疵的演算法。在第一個階段中，我們對違反時脈限制的路徑插入緩衝器，或者是改變這些路徑上邏輯閘的大小來達到符合時脈限制的目的。在第二個階段中，我們更進一步使用技術映射的技巧將違反時脈限制區域的線路重新映射。我們的演算法對五個工業界的測試檔案可以修正99.86%的違反時序總計值(total negative slack)，而且我們的演算法的執行時間也相當優異，表示我們的方法是相當有效的。

Spare cells rewiring is a technique used to fix defects or deficiencies after the placement stage. It is traditionally done by manual work but becomes extremely hard nowadays. In this thesis, we propose the first spare cells selection algorithm consisting of two phases to optimize timing of the circuit by rewiring spare cells. In the first phase, we apply gate sizing and buffer insertion to all timing violated paths to fix timing violations. In the second phase, we further fix timing violations by extracting timing critical parts and apply technology remapping to them. Experimental results based on five industrial benchmarks show that our algorithm can fix up to 99.82\% of the total negative slack, and the runtime is very short. The experimental results show that our algorithm is efficient and effective.