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標題: | 寬頻功率放大器與除頻器之研製 Design and Implementations of Broadband Power Amplifiers and Frequency Dividers |
作者: | Mei-Chen Chuang 莊嵋箴 |
指導教授: | 王暉 |
關鍵字: | 功率放大器,除頻器, Power amplifier,divider, |
出版年 : | 2006 |
學位: | 碩士 |
摘要: | 本論文主要是討論寬頻微波通訊系統之寬頻功率放大器與應用於鎖相迴路之除頻器。
在接收器中,功率放大器是一個重要的元件,而寬頻之功率放大器在設計上擁有難度。而利用分散式放大器,可以使得頻寬增加。在此論文中介紹了兩個寬頻的功率放大器,其特色為寬頻、高增益、中等功率、和好的增益平坦度。 本論文中設計兩個寬頻功率放大器,一個是利用砷化鎵0.15微米製程之4-37-GHz之寬頻功率放大器。此電路為利用兩級串接之分散式功率放大器,來達到高輸出功率,並藉由匹配來完成此一設計。另一個為利用砷化鎵0.15微米製程設計之15-50-GHz之寬頻功率放大器。此電路為利用兩極串接之分散式放大器來提供頻寬與增益,並且串接單級之放大器於輸出級。並且利用減少分散式放大器之級數和級與級之間的匹配來達到平坦的增益和減少直流功率損耗。 鎖相迴路技術已發展多年並且常來實現一個好的本地振盪源。而除頻器是實現高頻鎖相迴路之設計瓶頸。因傳統除頻器是用數位觸發器所實現,而此架構並不適用於高頻運作。本論文將探討高頻的除頻器架構,如注入鎖定式及正反饋式除頻器。 本論文中亦設計了兩個除頻器,一個利用台積電CMOS 0.18微米製程所設計之30GHz除四除頻器,此電路採取再利用電流之方式,使得可以節省功率並且因為元件之減少而可以縮小面積。另外一個也是採取台積電CMOS製程所設計之50GHz除四之除頻器,此電路採取匹配之方法,來達到可以直接在饋入四倍頻之訊號而可以達到除四的效果。並且可以利用很小的面積,達到此效果。 Researches on the broadband power amplifier for microwave wide band system and frequency divider for phase locked loops are presented in this dissertation. Power amplifier is an essential building block in transmitter system. Broadband power amplifier is not easy to design. Using distributed amplifier as the architecture can achieve wide band. Two broadband Pas are designed and implemented, and they achieve broadband, high gain, medium power and gain flatness. A 4-37GHz broadband power amplifier using 0.15μm has been design and fabricated. The circuit cascades two distributed power amplifier for higher output power. The other is a 15-50GHz broadband power amplifier. This circuit cascade two distributed amplifier and a single-stage amplifier as the output. Reducing the stage of the distributed amplifier and using interstage matching network can reduce the dc power consumption and achieves flat gain. Phase-locked loop (PLL) technique has been developed for decades and is the most frequently adopted to realize a high-quality LO source. Frequency divider is the design bottleneck for high frequency PLL since the conventional flip-flop based structure is not suitable for high-speed operation. In this thesis, high speed frequency divider topologies, such as injection locked frequency divider and regenerative frequency divider are investigated. A 30-GHz divided-by-four frequency divider fabricated using TSMC 0.18-μm CMOS has been designed and fabricated. The circuit adopts current-reuse method to reduce dc power and size of the layout due to less components needed. A 50-GHz divided-by-four frequency divider fabricated using TSMC 0.18μm CMOS. Using matching networks, these circuits achieve divide-by-four function directly with the small chip size. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/33028 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
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