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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Feipei Lai) | |
| dc.contributor.author | CHUN-HSIN LIEN | en |
| dc.contributor.author | 連俊鑫 | zh_TW |
| dc.date.accessioned | 2021-06-13T04:11:24Z | - |
| dc.date.available | 2006-07-31 | |
| dc.date.copyright | 2006-07-31 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-25 | |
| dc.identifier.citation | [1] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics Magazine, vol. 38, pp. 114–117, April 1965.
[2] National Technology Roadmap for Semiconductors, 1997. [3] Mustafa Celik, Lawrence Pileggi, Altan Odabasioglu. IC Interconnect Analysis. Kluwer Academic Publishers, 2001. [4] Dennis Sylvester, Kurt Keutzer, “Impact of small process geometries in system on chip,” in Proceedings of the IEEE, 2001. [5] S. Borkar, “Design Challenges Of Technology Scaling,” in Micro, IEEE, 1999. [6] J. Cong, “A interconnect-centric design flow for nanometer technologies,” Proceedings of the IEEE, vol. 89, no. 4, pp. 505–528, Apr. 2001. [7] S. Tarafdar and M. Leeser, “The DT-model: High-level synthesis using data transfers,” in Proceedings - Design Automation Conference, 1998. [8] C. Jego, E. Casseau, and E. Martin, “Interconnect cost control during high-level synthesis,” in Proceedings - Design Automation Conferenc, 2000. [9] J. A. Davis et al. “Interconnect Limits on Gigascale Integration (GSI) in the 21st Century,” Proceedings of the IEEE, March 2001. [10] M. Pedram, “Power Minimization in IC Design: Principles and Applications”, ACM transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, Jan., 1996. [11] S. P. Khatri, A. Mehrotra, R. K. Brayton, A. S. Vincentelli and R. H. J. M. Otten, “A Novel VLSI Layout Fabric for Deep Sub-Micron Applications,” in Proceedings - Design Automation Conference, 1999. [12] Y. Massoud et al., “Layout techniques for minimizing on-chip interconnect self inductance,” in Proceedings - Design Automation Conferenc, pp. 566–571, June 1998. [13] A. Deutsch et al., “When are transmission-line effects important for on chip interconnections,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836–1846, Oct. 1997. [14] M. Lee, A. Hill, and M. H. Darley, “Interconnect inductance effects on delay and crosstalks for long on-chip nets with fast input slew rates,” in Proc. Int. Symp. Circuits and Systems, May 1998. [15] El-Moursy, Magdy A., “Shielding effect of on-chip interconnect inductance,” Transactions on Very Large Scale Integration (VLSI) Systems, v 13, n 3, March, 2005. [16] M. Satar, et al., “Delay and noise estimation of CMOS logic gates driving coupled RLC submicron interconnections,” Proceedings of Modelling and Simulation, MS'2004, 2004. [17] BENINI, L., DE MICHELI, G., AND MACII, E., “Designing low-power circuits: Practical recipes,” IEEE Circuits and Systems Magazine 1, 1 (March), 6–25, 2001. [18] R. Mehra, L. M. Guerra, and J. Rabaey, “Low-power architectural synthesis and the impact of exploiting locality,” in Journal of VLSI Signal Processing, 1996. [19] L. Zhong and N. K. Jha, “Interconnect-aware high-level synthesis for low power,” in Proceedings - Design Automation Conferenc, 2002. [20] M.R. Stan and W. P. Burleson, “Bus-Invert Coding for Low-Power I/O,” in IEEE Trans. on VLSI Systems, 1995. [21] M Madhu, VS Murty, V Kamakoti, “Dynamic coding technique for low-power data bus,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2003. [22] M Saneei, A Afzali-Kusha, Z Navabi, “Sign bit reduction encoding for low power applications,” in Proceedings - Design Automation Conference, 2005. [23] C. Alpert, A. Devgan, and S. Quay, “Buffer Insertion for Noise and Delay Optimization,” in Computer-Aided Design of Integrated Circuits and Systems, 1999. [24] L. He and K. M. Lepak, “Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization,” in ACM Transactions on Design Automation of Electronic Systems, 2004. [25] Mohamed A. Elgamel and Magdy A. Bayoumi, “Efficient shield insertion for inductive noise reduction in nanometer technologies,” in Transactions on Very Large Scale Integration (VLSI) Systems, March, 2005. [26] Chan, Hsin-Yi, “A Selective Shield Insertion Algorithm for Low Power Bus,” in NTU CSIE Master Theme, 2004. [27] Bakoglu, H. B. Circuits, Interconnections, and Packaging for VLSI. Addsion-Wesley, 1990. [28] Dr. Eric Bogatin. What Really Is Inductance?. Bogatin Enterprises Oct 30, 1999. [29] A. E. Ruehli, “Inductance Calculations in a Complex Integrated Circuit Environment,” IBM Journal of Research and Development, 1972. [30] Y. Massoud, et al., “Layout Techniques for Minimizing On-Chip Interconnect Self Inductance,” in Proceedings - Design Automation Conferenc, 1998. [31] K Nabors, J White, “FastCap: a multipole accelerated 3-D capacitance extraction program,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 1991. [32] M Kamon, MJ Ttsuk, JK White, “FASTHENRY: a multipole-accelerated 3-D inductance extractionprogram,” in IEEE Trans. Microwave Theory Tech., 1994. [33] D. Burger, T. M. Austin, “The SimpleScalar Tool Set 2.0,” http://www.simplescalar.com, 1997. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32538 | - |
| dc.description.abstract | 當晶片設計進入深次微米世代，金屬導線已逐漸成取代邏輯閘延遲而為效能設計上的瓶頸，尤其當工作頻率達到Giga Hz以上時，除了導線間電容造成的雜訊外，導線間寄生電感帶來的效應更是不可忽視。為了降低導線間寄生效應產生的雜訊及功耗，插入屏蔽線是個有效的方法。本篇論文在同時考慮寄生電容、電感模型下，針對指令位址匯流排提出了一個決定屏蔽線插入位置的演算法。它根據匯流排上每一條位元線的內容變換量以及匯流排全部的總內容變換量，將原先的匯流排分割出數個區塊，再從每個區塊中，利用HSPICE模擬的結果作為準則，找出最佳的屏蔽線插入位置。實驗結果顯示，我們的方法在降低功耗及延遲上，成果大約是SSIA方法的1.6倍。其中當插入四條屏蔽線時，較未插入任何屏蔽線的情況下節省了12.83% 的功耗，在時間延遲上亦減少了1.76%。 | zh_TW |
| dc.description.abstract | With the integrated circuits technology entering the era of deep sub-micron, the interconnections on the chip have become the performance bottleneck. The situation is especially obvious when the operating frequency is at several giga Hz because not only the parasitic capacitances result in noise but also the coupling inductances incur the signal integrity problem. In order to reduce the undesired noise and power consumption caused by parasitic elements between wires, shield insertion is a common and effective approach. In this theme, we proposed an algorithm to decide the shield insertion locations under the consideration of both capacitive and inductive coupling impacts. It partitions the whole instruction address bus into some regions according to the coupling effects between every two adjacent signal wires and finds the best shielding location based on HSPICE simulation results. Experimental results show that our method can reduce the power consumption and delay up to 1.6 times the achievements of SSIA. In the case of four shields, there is a 12.83% reduction on power consumption as well as a 1.76% reduction on delay compared to the case without any shield. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T04:11:24Z (GMT). No. of bitstreams: 1 ntu-95-R93922119-1.pdf: 393509 bytes, checksum: ab815311f5166ccbb610c4ac7f936f38 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Interconnect Trends 1 1.2 Motivation 3 1.3 Related Work 4 1.4 Organization 6 Chapter 2 Background 7 2.1 Interconnect Capacitance 7 2.1.1 Self-Capacitance 7 2.1.2 Coupling Capacitance 11 2.2 Interconnect Inductance 15 2.2.1 Self-Inductance 15 2.2.2 Mutual Inductance 15 2.2.3 Loop Inductance 16 2.2.4 Partial Inductance 16 2.3 The shielding method 17 2.4 Selective Shield Insertion Algorithm 19 2.5 The RLC Model 26 2.5.1 The Lumped Model 26 2.5.2 The distributed RLC model 27 Chapter 3 Proposed Low Power Shielding Method for Address Bus 28 3.1 Problem Formulation 28 3.2 Proposed Method 29 3.2.1 Statistical Characterization 31 3.2.2 Partition the Bus 33 3.2.3 Getting Final Shield Locations Overall 38 Chapter 4 Experimental Results 39 4.1 Experimental Environment 39 4.2 Experimental Flow 39 4.3 Experimental Results 41 Chapter 5 Conclusion 45 Bibliography 46 | |
| dc.language.iso | en | |
| dc.title | 以屏蔽線插入法為基礎之低功率指令位址匯流排設計 | zh_TW |
| dc.title | Shield Insertion Based Low Power Instruction Address Bus Design | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊佳玲(Chia-Lin Yang),顧孟愷(Mong-kai Ku),陳澤雄(Tzer Shyong Chen),張延任(Yen-Jen Chang) | |
| dc.subject.keyword | 屏蔽線插入法,功耗,雜訊,耦合效應, | zh_TW |
| dc.subject.keyword | Shield insertion,power consumption,noise,coupling effect,HSPICE, | en |
| dc.relation.page | 48 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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