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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 曹恆偉 | |
dc.contributor.author | " Ching-Sheng,Wu" | en |
dc.contributor.author | 吳慶昇 | zh_TW |
dc.date.accessioned | 2021-06-13T03:40:35Z | - |
dc.date.available | 2008-07-31 | |
dc.date.copyright | 2006-07-31 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-26 | |
dc.identifier.citation | chapter2
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[17] “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS” Staszewski, R.B.; Muhammad, K.; Leipold, D.; Chih-Ming Hung; Yo-Chuol Ho; Wallberg, J.L.; Fernando, C.; Maggio, K.; Staszewski, R.; Jung, T.; Jinseok Koh; John, S.; Irene Yuanying Deng; Sarda, V.; Moreira-Tamayo, O.; Mayega, V.; Katz, R.; Friedman, O.; Eliezer, O.E.; de-Obaldia, E.; Balsara, P.T.;Solid-State Circuits, IEEE Journal ofVolume 39, Issue 12, Dec. 2004 Page(s):2278 - 2291 Digital Object Identifier 10.1109/JSSC.2004.836345 [18] R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara, “Digitally-controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicron CMOS process,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 815–828, Nov. 2003. [19] Staszewski, R.B.; Leipold, D.; Chih-Ming Hung; Balsara, P.T.“TDC-based frequency synthesizer for wireless applications” Radio Frequency Integrated Circuits (RFIC) Symposium, 2004. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/32282 | - |
dc.description.abstract | 在現今無線通訊系統中,系統功率消耗的考量是個重要課題,而發射端的功率放大器是消耗大量功率的元件。在較早期的通訊標準,發射信號的包絡(envelope)是定值,我們可以在發射端使用非線性但高功率效益的功率發大器。但在GSM/EDGE及WCDM的標準之後,包絡(envelope)不再是定值,在發射端我們就需要一個線性放大的功率放大器,而這樣的功率放大器效率就會被犠牲掉。功率放大器的線性化技術可以改善發射機的線性度和效率,而在眾多線性化的技術中,LINC技術能夠讓系統採用高效率的非線性功率放大器來進行線性放大,因而提升了發射機的線性度和效率。
但LINC 架構的發射機也有LINC帶來的問題,比如經過非線性的信號轉換,信號頻寬會被大幅放大,信號頻寬的放大對相位調變的調變器(phase modulator) 是個很大的挑戰。而LINC兩路信號之間的相位(phase)和增益(gain)不匹配,也會使傳輸信號失真而不符合系統規範的要求。 在本論文中,我們修改了TI提出的全數位相位調變發射機的架構,使其能傳輸LINC寬頻信號,而且使用模擬的方式驗證其能符合WCDMA的規範。在比較了文獻提出的解決增益/相位不匹配的方案後,我們提出了新的修正架構,能以較少的成本而有效的消除增益/相位不匹配的問題。 | zh_TW |
dc.description.abstract | In a modern wireless communication system, the system power consumption is an important issue, and the power amplifier (PA) is a very power-hungry device in the transmitter. In the early communication standard, envelope of the transmitting signal is constant and we can use non-linear but high efficiency PA in the transmitter. However, after the GSM/EDGE and WCDMA standard, the envelope of signal is not constant. It means that we need a linear PA, but there is a trade off between linearity and efficiency. There are many linearity techniques proposed to improve the linearity and efficiency of PA. LINC can make the transmitter use non-linearly but high efficiency PA to linearly amplify the signal and then improve the linearity and efficiency of the transmitter.
However, the LINC transmitter has some particular problems. After LINC transform, the bandwidth of the signal will be extended largely. The wide band signal is a big challenge to the phase modulator. The gain/phase mismatch between two loops will distort the signal and the distorted signal can’t meet the spec. We modify the architecture of all-digital phase modulation transmitter proposed by TI, and make it be able to transmit the wide band WCDMA LINC signal. We use simulation to verify it meets the transmitter specification of WCDMA. After surveying some gain/phase mismatch solutions, we propose a new architecture which can use lower hardware cost but reduce the gain/phase mismatch efficiently. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T03:40:35Z (GMT). No. of bitstreams: 1 ntu-95-R93942101-1.pdf: 6461241 bytes, checksum: 737626afb849fbc6077230809e813ca3 (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | 摘要 I
章節簡介 IV Chapter 1 iv Chapter 2 iv Chapter 3 iv Chapter 4 iv Chapter 5 v Chapter 6 v Chapter 7 v ABSTRACT VI INDEX VII LIST OF FIGURES X LIST OF TABLES XIV 1. INTRODUCTION 1 1.1. MOTIVATION 1 1.2. OUR CHALLENGE 2 1.3. ORGANIZATION IN THIS THESIS 2 2. BASIC CONCEPTS 5 2.1. METHODS OF FREQUENCY MODULATION UPCONVERSION 5 2.2. BEHAVIOR OF AN IDEAL LINEAR PA 6 2.3. SQUARE LAW AND THIRD ORDER CHARACTERISTIC OF PA 7 2.4. VARYING ENVELOPE AND CONSTANT ENVELOPE SIGNALS 9 2.5. METHODS OF POWER AMPLIFIER LINEARIZATION 10 2.5.1. Polar Architecture 10 2.5.2. Linear Amplification with Nonlinear Components (LINC) 14 3. LINC TRANSMITTER SYSTEM OVERVIEW 17 3.1. LINC MATHEMATICAL MODEL 17 3.1.1. The I/Q Modulation Method [5] 17 3.1.2. The Phase Modulation Method 19 3.2. LINC COMPONENT DESCRIPTION 21 3.2.1. Signal Component Separator (SCS) 21 3.2.2. Modulator 21 3.2.3. Power Amplifier (PA) 22 3.2.4. Power Combiner [6] 22 3.3. REVIEW OF THE SYSTEM ARCHITECTURES OF LINC TRANSMITTER 23 3.3.1. Conventional Analog LINC Architecture 24 3.3.2. Inpahse / Quadrature Method Architecture 26 3.3.3. Phase Modulation Method [10] 26 3.4. PROPOSED LINC TRANSMITTER ARCHITECTURE 29 4. ALL-DIGITAL PLL (ADPLL) SYNTHESIZER OVERVIEW 31 4.1. ADPLL-BASED RF FREQUENCY SYNTHESIZER 31 4.1.1. Reference Clock Retiming 32 4.1.2. Phase-domain Operation 33 4.1.3. Phase Detection 35 4.2. IMPORTANT BLOCKS IN ADPLL 36 4.2.1. Digitally Controlled Oscillator (DCO) 36 4.2.2. Time-to-Digital Converter (TDC) [19] 44 4.2.3. Sigma-delta Modulator 46 4.3. DISCRETE-TIME Z-DOMAIN MODEL 51 4.4. TWO-POINT DIRECT MODULATION SCHEME 53 5. WCDMA TRANSMITTER DESIGN 55 5.1. CHARACTERISTICS OF WCDMA [21][22][23] 55 5.2. SIGNAL PROPERTY OF THE LINC SYSTEM 57 5.3. REFERENCE FREQUENCY DECIDE 60 5.4. SIGMA-DELTA MODULATOR DESIGN 67 5.4.1. Multi-stage Noise Shaped (MASH) Structure 68 5.4.2. Phase Noise due to Sigma-delta Dithering 69 5.4.3. Modified Sigma-delta Modulator 73 5.5. TDC DESIGN 78 5.6. DCO CORE DESIGN 80 5.7. NOISE AND ERROR SOURCES 90 5.7.1. Z-domain Model of the Type-2 ADPLL 90 5.7.2. The Phase Noise Analysis 92 6. NONLINEAR DISTORTION CANCELLATION USED IN THE LINC TRANSMITTER 103 6.1. DELAY AND GAIN MISMATCH TOLERANCE 103 6.2. GAIN/PHASE MISMATCH CANCELLATION TECHNIQUE SURVEY [29]~[34] 106 6.2.1. Foreground Calibration Algorithm [32] 106 6.2.2. Background Calibration Algorithm [33] 107 6.2.3. Adaptive Signal Processing Technique [34] 110 6.3. ADPLL TRANSMITTER WITH GAIN/PHASE MISMATCH CALIBRATION 112 6.3.1. Quadrature Modulator 112 6.3.2. Phase Modulator 121 7. CONCLUSION 127 REFERENCE 129 | |
dc.language.iso | en | |
dc.title | 適用於WCDMA全數位寬頻調變迴路之LINC發射機架構設計 | zh_TW |
dc.title | LINC Transmitter for WCDMA Using All Digital Wideband Modulation Loops | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李揚漢,吳安宇,黃天偉 | |
dc.subject.keyword | 全數位,鎖相迴路, | zh_TW |
dc.subject.keyword | ADPLL,WCDMA,LINC,transmitter, | en |
dc.relation.page | 131 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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