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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉 | |
dc.contributor.author | Tz-Cheng Yang | en |
dc.contributor.author | 楊子承 | zh_TW |
dc.date.accessioned | 2021-06-13T03:26:26Z | - |
dc.date.available | 2011-07-31 | |
dc.date.copyright | 2006-07-31 | |
dc.date.issued | 2006 | |
dc.date.submitted | 2006-07-28 | |
dc.identifier.citation | [1] R. E. Best, “Phase-Locked Loops, ” 5th Ed., McGraw-Hill, 2003.
[2] W. F. Egan, “Phase-Lock Basics,” Wiley-Interscience, 1998. [3] B. Razavi, “Design of Analog CMOS Integrated Circuirs,” McGraw-Hill, 2001. [4] B. Razavi, 'RF Microelectronics,” Prentice Hall, 2003. [5] B. Razavi, “Design of Integrated Circuits for Optical Communications,” 1st Ed., McGraw-Hill, 2003. [6] Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-μm CMOS Technology,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 56 - 62, 12-14 June 2003. [7] Garth Nash, “Phase-Locked Loop Design Fundamentals,” Freescale Semiconductor Application Note, 2006. [8] Jri Lee and Shanghann Wu, “Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 140 - 143, 16-18 June 2005. [9] Kuo-Hsing Cheng, Wei-Bin Yang, and Cheng-Ming Ying, “A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 50, no. 11, pp. 892 - 896, November 2003. [10] Payam Heydari, “Design and Analysis of Low-Voltage Current-Mode Logic Buffers,” Fourth International Symposium on Quality Electronic Design, pp. 293 - 298, 24-26 March 2003. [11] Michael Perrott, “High Speed Communication Circuits and Systems Lecture 14 High Speed Frequency Dividers,” Massachusetts Institute of Technology, 2003. [12] Dean Banerjee, “PLL Performance,” National Semiconductor. [13] Mark Clements, Kasin Vichienchom and Wentai Liu, “Improved Frequency Synthesizer Phase Noise Performance Using CMOS Delay Verniers,” ERL Technical Report, September 1999. [14] Garth Nash, “Phase-Locked Loop Design Fundamentals,” Motorola Inc. Applications Note, 1994. [15] K. Arshak, O. Abubaker, E. Jafer, “Design and Simulation Difference Types CMOS Phase Frequency Detector for high speed and low jitter PLL,” Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, Dominican Republic, pp. 188 - 191, 3-5 November 2004. [16] Amit Mehrotra, “Noise Analysis of Phase-Locked Loops,” IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1309 - 1316, September 2002. [17] Robert C. Chang and Lung-Chih Kuo, “A Differential-Type CMOS Phase Frequency Detector,” The Second IEEE Asia Pacific Conference on ASICs, pp. 61 - 64, 28-30 August 2000. [18] Frank Herzel and Behzad Razavi, “A Study of Oscillator Jitter Due to Supply and Substrate Noise,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, vol. 46, no. 1, pp. 56 - 62, January 1999. [19] José Manuel Cazeaux, Martin Omaña and Cecilia Metra, “Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs,” IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 5, pp. 1779 - 1788, October 2005. [20] Ken Kundert, “Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers,” Designers Guide Consulting, Inc., November 2005. [21] Rick Poore, “Phase Noise and Jitter”, Agilent EEsof EDA, May 2001. [22] Thomas H. Lee and Ali Hajimiri, “Oscillator Phase Noise: A Tutorial,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 326 - 336, March 2000. [23] Li Lin, Luns Tee, Paul R. Gray, “A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture,” IEEE International Solid-State Circuits Conference, pp. 204-205, February 2000. [24] Jeffrey A. Weldon, R. Sekhar Narayanaswami, Jacques C. Rudell, Li Lin, Masanori Otsuka, Sebastien Dedieu, Luns Tee, King-Chun Tsai, Cheol-Woong Lee and Paul R. Gray, “A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter With Harmonic-Rejection Mixers,” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 2003 - 2015, December 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31972 | - |
dc.description.abstract | 隨著無限通訊系統的快速發展,對於具有高精確度鎖相迴路的需求也
隨著顯著增加。不僅如此,在鎖相迴路中的輸出相位雜訊對本地震盪器而 言是一個非常重要的性能指標,因為相位雜訊的好壞會影響到整體接收訊 號的品質。相位雜訊差,將會干擾到鄰近通道的訊號產生嚴重的收發問題。 本篇論文的目標即在實現一個適用於40~48 GHz超寬頻系統的低相位 雜訊18.5 GHz鎖相迴路。除了一個常見的高速架構外,我們也會提出一個 使用全差動頻率相位偵測器的改良型鎖相迴路,並且將會探討兩者間的性 能差異。 | zh_TW |
dc.description.abstract | With the rapid growing of the wireless communication system, the demands of high precision phase-locked loops (PLLs) increase significantly. Besides, output phase noise of PLLs is very important for local oscillator. It is because that the quality of phase noise would influence bith transmitting and receiving chain seriously.
This thesis will aim to implement an 18.5 GHz PLL with improved phase noise for 40~48 GHz UWB system. We will propose two architectures which are a common high speed phase-locked loop and an improved fully differential phase-locked loop. The performance of both architectures will be compared. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T03:26:26Z (GMT). No. of bitstreams: 1 ntu-95-R92943062-1.pdf: 10411049 bytes, checksum: 98155cda469d2be0ed0a0fe38e57c41b (MD5) Previous issue date: 2006 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Ultra-Wideband Overview 2 1.2 Motivation and Research Goals 6 1.3 Thesis Overview 7 Chapter 2 Phase-Locked Loops Fundamentals 9 2.1 Phase-Locked Loops Basics 9 2.2 Type-Order 13 2.3 Error Constants 13 2.4 Stability 16 2.5 Bandwidth 22 2.6 Phase-Locked Loops Performance 22 2.6.1 Phase Noise 23 2.6.2 Spurs 25 2.6.3 Lock Time 27 2.6.4 Loop Bandwidth 28 2.6.5 Fastlock 28 2.6.6 RMS Phase Error 29 Chapter 3 Circuit Architecture and Implementation 33 3.1 Phase/Frequency Detector 33 3.2 Charge Pump 41 3.3 Loop Filter 44 3.4 Frequency Divider 50 3.4.1 Miller Divider 51 3.4.2 CML Master-Slave DFF Static Divider 56 3.5 Differential to Single-ended Converter 60 3.6 VCO 61 3.7 PLL Closed-Loop Simulation 62 3.8 Layout and Floorplan 65 Chapter 4 An Improved Fully Differential Phase-Locked Loop 67 4.1 A Differential-Type Phase Frequency Detector 68 4.2 VCO 76 4.3 Fully Differential PLL Closed-Loop Simulation 77 4.4 Layout and Floorplan 81 Chapter 5 Test and Measurement 83 5.1 Measurement Configuration of PLL With Air Cavity Resonator 84 5.2 Measurement Configuration of PLL with LTCC Cavity Resonator 85 5.3 Measurement Procedures 86 Chapter 6 Conclusion 87 Reference 89 | |
dc.language.iso | en | |
dc.title | 適用於40~48GHz超寬頻系統之18.5GHz全差動式鎖相迴路 | zh_TW |
dc.title | A 18.5GHz Fully Differential Phase Lock Loop for 40~48GHz UWB System | en |
dc.type | Thesis | |
dc.date.schoolyear | 94-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張鴻埜,呂良鴻,呂學士 | |
dc.subject.keyword | 差動,鎖相迴路,超寬頻,相位雜訊, | zh_TW |
dc.subject.keyword | PLL,UWB,differential,phase noise,jitter, | en |
dc.relation.page | 90 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2006-07-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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