以模擬為基礎產生影像處理編解碼器之驗證圖樣

Abstract

隨著積體電路製成的逐漸縮小，單一晶片內所能夠包含的功能也越來越複雜，而系統單晶片設計遂逐漸蔚為潮流。而在整著設計流程中，驗證所消耗的時間，往往佔了整個流程的70%~80%，成為整個設計的瓶頸。 在一般的設計過程中，通常會先以比較高階的語言，例如C/C++，完成設計，在確認無誤後，再轉為暫存器轉換語言。從高階語言轉換至較為低階語言的過程中，程式碼所隱藏的錯誤，也將被埋置更深處，而更不容易被找到。 本文即是針對高階語言所撰寫而成的影像處理程式，提出一套方法，來提高程式碼的品質。確保將來的轉換無誤，以及減少程式碼錯誤傳遞，進而提高程式正確運作的機率，降低日後的除錯成本。在這套方法中，我們以進階的模擬退火演算法來增加程式碼的覆蓋率，並藉由覆蓋率的提高，來加強程式品質。除此之外，設計者也可針對某一部份的程式碼，來做比較嚴格的測試。傳統上，一般使用的測試圖樣對於程式碼而言，是無法改變程式碼的覆蓋程度。然而在本文中，設計者可以針對某一部份程式，在合理的限制條件之下，做更嚴格的覆蓋率測試。

In the IC design process, verification usually accounts for 70% ~ 80% times of the whole design procedure and has become the main design bottleneck[2]. In general, the IC design process starts with high level computer language like C/C++ which are then transformed into RTL (Register-Transfer Level) code. In the transformation, programming errors, called bugs, will be propagated and hid more deeply in the bulk codes and this bug-propagation makes debug more difficult in the future verification procedure. In this thesis, we propose a verification pattern generation method which ensures the C/C++ program quality and thus lowers the debug cost in the succeeding design stages. In this thesis, we propose a simulation-based verification pattern generation technique for image codec. To guarantee the correctness of their image codec, the designers usually use pictures like Lena as the verification pattern. However, the verification quality is not guaranteed. To resolve this problem, the proposed pattern generation technique synthesizes the verification pattern according to a pre-defined block template. Compared to past approaches, e.g., Lena or random pictures, the proposed technique has two advantages. First, with much less pattern size (less than 20 vs. more than 2,000 blocks), better or the same code coverage figures are achieved. Second, the proposed method allows the user to specify the desired coverage profile to better fit his or her verification goal.