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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31678完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
| dc.contributor.author | Shu-Jau Chang | en |
| dc.contributor.author | 張書照 | zh_TW |
| dc.date.accessioned | 2021-06-13T03:17:21Z | - |
| dc.date.available | 2008-08-01 | |
| dc.date.copyright | 2006-08-01 | |
| dc.date.issued | 2006 | |
| dc.date.submitted | 2006-07-30 | |
| dc.identifier.citation | [1] R. D. Isaac, “The future of CMOS technology,” IBM J. Res. Develop., Vol.44, no.3, p.369-378, May. 2000.
[2] Dave Bursky, “Innovation, not scaling key to future ICs, says IBM exec,” http://www.eetimes.com/news/latest/technology/showArticle.jhtml?articleID=181401248, EE Times, 28 Feb. 2006. [3] “ITRS 2005 Edition,” http://www.itrs.net/Links/2005ITRS/Home2005.htm. [4] Y. P. Lin., “Application of anodization in the study of interfacial suboxide characteristics and high-k gate dielectric in MOS device,” p. 5-21, Jan. 2004. [5] F. Giustino and A. Pasquarello, “Electronic and dielectric properties of a suboxide interlayer at the silicon–oxide interface in MOS devices,” Surface Science, vol. 586, p.183-191, Jul. 2005. [6] C. -H. Lin, B. -C. Hsu, M. H. Lee, and C. W. Liu, “A comprehensive study of inversion current in MOS tunneling diodes,” IEEE Trans. Electron Devices, vol.48, no.9, p.2125-2130, Sep. 2001. [7] E. Kameda et al., “Fowler-Nordheim tunneling in MOS capacitors with Si-implanted SiO2,” Solid-State Electronics, vol.42, no.11, p.2105-2111, 1998. [8] D. Ielmini et al., “A recombination- and trap-assisted tunneling model for stress-induced leakage current,” Solid-State Electronics, vol.45, p.1361-1369, 2001. [9] M. Y. Doghish and F. D. Ho, “A comprehensive analytical model for metal insulator semiconductor (MIS) devices,” IEEE Trans. Electron Devices, vol.39, p.2771, 1992. [10] G. Lucovsky, “Atomic structure and thermal stability of silicon suboxides in bulk thin films and in transition regions at Si–SiO2 interfaces,” Journal of Non-Crystalline Solids, p.227-230, 1998. [11] P. Bulk, “The Si-SiO2 System,” Elsevcir Sci. Pub., p.10, p.15, 1988. [12] F. J. Morin and J. P. Maita, “Electrical properties of silicon containing arsenic and boron,” Phys. Rev., vol.96, p.28-35, 1954. [13] Stephen A. and Campell, “The Science and Engineering of Microelectronic Fabrication,” Oxford University Press, p.42, 1996. [14] Y. H. Shin, “The study of MOS devices with ultra-thin gate oxides and their temperature detection applications,” PP. 30-67, Dec. 2001. [15] F. Herman, J. P. Batra, and V. Kasowahi, “The Physics of SiO2 and Its Interfaces,” Pergamon Press, New York, 1978, p.333 (Ed. S. Pantelides). [16] E. H. Nicollian and J. R. Brews, “MOS (Metal Oxide Semiconductor) Physics and Technology,” 1982. [17] Maxim Ershov, H. C. Liu, L. Li, M. Buchanan, Z. R. Wasilewski, and Andrew K. Jonscher, “Negative capacitance effect in semiconductor devices,” IEEE trans Electron Devices, vol.45, no.10, Oct. 1998. [18] Mieko Matsumura and Yutaka Hirose, “Negative-capacitance effect in forward-biased metal oxide semiconductor tunnel diodes (MOSTD),” Jpn. J. Appl. Phys. Lett., vol.39, p.L123-L125, 2000. [19] Yasushi Okawa, Hideyuki Norimatsu, Hiroyuki Suto, and Mariko Takayanagi, “The negative capacitance effect on the C-V measurement of ultra thin gate dielectrics induced by the dtray capacitance of the measurement system,” IEEE ICMTS, p.197-202, 2003. [20] Hiroyuki Suto, Satoshi Inaba, and Kazunari Ishimaru, “Error evaluation of C-V characteristics measurements in ultra-thin gate dielectrics,” IEEE ICMTS, p.221-226, 2004. [21] M. Chemla, V. Bertagna, R. Erre, F. Rouelle, S. Petitdidier, and D. Levy, “Thickness of surface thin oxide layers determined by impedance spectroscopy using silicon/oxide/electrolyte (SOE) structures,” Applied Surface Science, vol.227, p.193-204, Apr. 2004. [22] Zhijiong Luo and T. P. Ma, “A new method to extract EOT of ultrathin gate dielectric with high leakage current,” IEEE Electron Device Lett., vol.25, no.9, Sep. 2004. [23] Jung-Suk Goo, Tilo Mantei, Karsten Wieczorek, William G. En, and Ali B. Icel, “Extending two-element capacitance extraction method toward ultraleaky gate oxides using a short-channel length,” IEEE Electron Device Lett., vol.25, no.12, Dec. 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31678 | - |
| dc.description.abstract | 為了要對P型及N型金氧半電容元件有更進一步的了解,針對不同的製程條件,我們同時生長P型和N型的矽晶片之氧化層,並做成金氧半電容元件。在量測電壓與電流的關係時,發現兩種元件的電流對厚度有不同的相依性,且於薄氧化層時,N型金氧半電容元件中反轉區電流對溫度的響應遠小於P型元件。最主要的原因是因為N型元件在反轉區的電流受控於次氧化層中,界面陷阱處所發生的電子與電洞復合機制,而P型元件則是受控於電子電洞產生機制。我們並利用由此差異性,將兩種元件串聯,N型元件相當於固定電流源,設計出一種有趣的溫度感測器。
在量測電壓與電容的關係時,發現N型元件薄氧化層的品質比P型元件好得多,即兩元件的氧化層都很薄時,N型元件的界面陷阱密度比P型少。這也是因為次氧化層在兩種元件扮演不同角色的關係。我們將生長氧化層的時間增加,相當於將次氧化層的品質改善後,發現兩種元件的差異性明顯地減小。另外,當生長的氧化層較薄時,偏壓加在空乏區進入反轉區的附近時,N型元件會量測出現負值電容。這是因為當偏壓在此附近時,會造成電子電洞對的大量復合,氧化層界面附近之儲存電荷減少,故造成負值電容的現象。而氧化層厚度增加,或是生長氧化層時間增加,此效應會減少許多。再次驗證次氧化層在比較P型與N型元件時,所扮演的角色是相當重要的。 | zh_TW |
| dc.description.abstract | For deeper understanding of p- and n-type MOS capacitor devices, we grew oxide on p- and n-type silicon substrates simultaneously with different recipes. When measuring current-voltage (J-V) characteristics, it was found that the oxide thickness dependencies of the current magnitudes of these two devices were different. Furthermore, with thin oxide films, the response of inversion saturation current to temperature in n-type MOS capacitors was much lower than that in p-type devices. The origin of these differences was mainly that the inversion saturation current in n-type devices was controlled by the recombination mechanism in interface traps located in sub-oxide, while the inversion saturation current in p-type devices was controlled by the generation mechanism. Based on the different current response to temperature of n-substrate MOS devices, we designed an interesting temperature sensor by connecting two devices in series, where n-type device was regarded as a constant current source.
When measuring capacitance-voltage (C-V) characteristics, it was found that the quality of the thin oxide film of n-type device was much better than that of p-type device. In other words, the interface trap density of n-type device is less than that of p-type device while both oxide films are very thin, which is strongly related to the sub-oxide. We improved the sub-oxide quality by increasing the growth time of oxidation, and then observed that the discrepancy between them became unapparent. Moreover, when the oxide film of n-type device was thinner, we found that negative capacitance occurred near the region when bias was changed from depletion to inversion. This is because when biasing in the neighborhood, lots of electron-hole pairs will start to recombine, which results in the stored charges near the interfacial layers decrease as the applied terminal voltage is increased. Again, when we increase the oxidation time, that is, thickening the oxide films, the negative-capacitance effect become unobvious. It is concluded that the sub-oxide plays an important role in the comparison of the characteristics of p- and n-type devices. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T03:17:21Z (GMT). No. of bitstreams: 1 ntu-95-R93943066-1.pdf: 1700004 bytes, checksum: 3c58a93d0c9d65cc4aaf410758b4d689 (MD5) Previous issue date: 2006 | en |
| dc.description.tableofcontents | Chapter 1 Introduction……………………….……………………...………1
1-1 Motivation……….…………………………………………………... 1 1-2 Scope of this work…………………………………………………....3 1-3 Experimental setup and measurement tools…………………………..4 Chapter2 Comparison of Current Conduction Mechanism………..6 2-1 Introduction…………………………………………………….……..6 2-2 Experimental design and device fabrication………………………….7 2-3 Results and discussions……………………………………….……....8 2-3-1 Oxide thickness dependency of J-V curves……………….....8 2-3-2 Temperature dependency of J-V curves………...…………..13 2-3-3 Current response to lightness…………….…………………16 2-4 Temperature sensor applications…………………………………….20 2-4-1 Operating principle …………...……………………………20 2-4-2 Design of measurement setup ……..……………………….21 2-4-3 Theoretical results and experimental observations……..…..22 2-5 Summary………………………………………….…………………25 Chapter 3 Comparison of Capacitance-Voltage (C-V) Characteristics………………………………………….26 3-1 Introduction………………………………………………………… 26 3-2 Results and Discussions……………………………………………..27 3-2-1 Comparison of interface trap density……………………….27 3-2-2 Capacitance response at low frequency……..……...………33 3-2-3 Investigation of negative capacitance occurred in n-type MOS capacitors…………..……………………………………….43 3-2-4 Modeling…………..………………………………………..50 3-3 Summary.…………………..………………………………………..58 Chapter 4 Conclusions……………...……………………………………….59 4-1 Conclusions………………………………………………………… 59 4-2 Suggestions and future work………………….……………………..60 References………………………………………………………………………....62 | |
| dc.language.iso | zh-TW | |
| dc.subject | 金氧半電容 | zh_TW |
| dc.subject | P型 | zh_TW |
| dc.subject | N型 | zh_TW |
| dc.subject | 溫度感測器 | zh_TW |
| dc.subject | 負電容 | zh_TW |
| dc.subject | MOS capacitor | en |
| dc.subject | negative capacitance | en |
| dc.subject | temperature sensor | en |
| dc.subject | n-type | en |
| dc.subject | p-type | en |
| dc.title | P型與N型金氧半電容元件於超薄氧化層之電特性比較及應用 | zh_TW |
| dc.title | Comparison of the Electrical Characteristics of MOS Capacitors with Ultra-thin Oxides Grown on P- and N-type Si Substrates | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 94-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 洪志旺,王維新,鄭晃忠 | |
| dc.subject.keyword | 金氧半電容,P型,N型,溫度感測器,負電容, | zh_TW |
| dc.subject.keyword | MOS capacitor,p-type,n-type,temperature sensor,negative capacitance, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2006-07-30 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位: | 電子工程學研究所 | |
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