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標題: | 即時單晶片系統之系統架構及排程整合演算法 System-Level Synthesis Algorithms for Real-Time SoC Design |
作者: | Yi-An Chen 陳奕安 |
指導教授: | 施吉昇(Chi-Sheng Shih) |
關鍵字: | 即時,單晶片,排程,軟硬體協同設計, real-time,SoC,scheduling,synthesis,system-level, |
出版年 : | 2006 |
學位: | 碩士 |
摘要: | 系統晶片的主要元件常常由處理器、特殊應用積體電路、矽智財等構成。使用哪些元件去整合成一個系統晶片對於該系統晶片的價錢、效能有非常大的影響。隨著製程不斷地進步,如何在系統層級決定一個系統晶片上的元件變成一個最重要的議題。以往的論文在運算層級討論整合演算法,在本篇論文中,我們在系統層級研究整合演算法,這些整合演算法決定了系統晶片上面硬體元件的配置、工作的分配,以及工作的排程。我們改良並比較了許多種類的整合演算法,包括指數式最佳演算法,重覆式演算法,建構式演算法,基因演算法等等。我們透過大量的模擬實驗呈現他們在不同的情況下各自的效能及結果。 System-on-a-Chips are usually synthesized by a number of ASICs, IPs, and (customized or general) microprocessors to reduce design overhead and manufacture cost. Which processing elements are chosen and how the chosen processing elements are assigned to complete the tasks have significant impacts on the cost and performance of the system. As the complexity of SoC increases, how to find an optimal system-level system architecture has became a critical issue for SoC design. Earlier researches focus on the system synthesis on operation level. In this thesis, we are concerned with system synthesis on system-level. The algorithms in this thesis determine the scheduling, allocating, and mapping on system-level. We compare the performance of several types of synthesis algorithms including exponential optimal algorithms, iterative heuristic algorithms, constructive heuristic algorithms, genetic-based algorithms. We shall present their performance for different task models. The result shows that the iterative heuristic algorithms can get the near optimal solution when there are not large number of instances. As the number of instances increases, the genetic algorithm outperforms the other algorithms on cost, and its mean run-time overhead is still acceptable. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31414 |
全文授權: | 有償授權 |
顯示於系所單位: | 資訊工程學系 |
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