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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Song-Yen Mao | en |
dc.contributor.author | 毛松彥 | zh_TW |
dc.date.accessioned | 2021-06-13T02:46:12Z | - |
dc.date.available | 2016-08-17 | |
dc.date.copyright | 2011-08-17 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-29 | |
dc.identifier.citation | [1] J. Gozalvez, “The European Union Backs the DVB-H Standard,” IEEE Vehicular Technology Magazine, Vol. 3, No.2, pp. 3–12, Jun. 2008.
[2] M.-C. Hsieh, “DSP Software Implementation of an IEEE 802.16-2004 Baseband Receiver,” Master Thesis, Dept. of Electrical Engineering, National Taiwan University, Taipei, Taiwan, Jun. 2010. [3] J. Kim., S.-H. Hyeon, and S.-W. Choi, “Implementation of an SDR System Using Graphics Processing Unit,” Communications Magazine, IEEE, Vol. 48, No.3, pp. 156-162, Mar. 2010. [4] IEEE Computer Society and IEEE Microwave Theory and Techniques Society, “IEEE Std 802.16-2001,” “IEEE Std 802.16a-2003,” “IEEE Std 802.16-2004,” “IEEE Std 802.16e-2005,” IEEE Standard for Local and Metropolitan area networks –Part 16: Air Interface for Fixed Broadband Wireless Access Systems. [5] nVidia. 2010. CUDA Programming Guide, version 3.1. [6] nVidia, “nVidia’s next Generation CUDA Compute Architecture: Fermi,” Production White Paper, 2009. [7] nVidia, “nVidia GF100: World’s Fastest GPU Delivering Great Gaming Performance with True Geometric Realism,” Production White Paper, 2009. [8] J. J. van de Beek and P. O. Borjesson, “A Time and Frequency Synchronization Scheme for Multiuser OFDM,” IEEE Journal on Selected Areas in Communications, Vol. 17, No.11, pp. 1900-1914, 1999. [9] P.-Y. Tsai, H.-Y. Kang, and T.-D. Chiueh, “Joint Weighted Least Squares Estimation of Frequency and Timing Offset for OFDM Systems over Fading Channels,” in Proc. IEEE Vehicular Technology Conference, Vol. 4, pp.2543-2547, Apr. , 2003. [10] T.-D. Chiueh and P.-Y. Tsai, OFDM Baseband Receiver Design for Wireless Communications. Taiwan, John Wiley & Sons, Inc., 2007. [11] C. Smith and J. Meyer, 3G Wireless with WiMAX and Wi-Fi: 802.16 AND 802.11, McGraw-Hill Professional Engineering, 2004. [12] A. Akapyev, V. Krylov, “Implementation of 802.11n on 128-Core Processor,” ISCA PDCCS, pp.56-60, Sep. 2008. [13] nVidia, “Optimizing Parallel Reduction in CUDA,” NVIDIA Developer Technology, 2008. [14] nVidia, “CUDA CUFFT Library,” NVIDIA Developer Technology, 2007. [15] Phillips, J.C., Stone, J.E., and Schulten, K., “Adapting a Message-Driven Parallel Application to GPU-Accelerated Clusters,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis, pp.1-9, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31373 | - |
dc.description.abstract | 在2008年時,中興電子(ZTE)宣布架設全球第一個以軟體定義無線電為基礎的基地台。軟體定義無線電(Software- Defined Radio)是為了能在單一設備上支援多重標準的解決之道,由於具有可重配置性(Reconfigurable),這種方式可以避免掉傳統上為了配合多規格而使用多套硬體的高成本,並且還能保有對未來新制定的規格之調適性。而在本論文中,我們提出適用於IEEE 802.16d OFDM標準的基地台端同步器架構,並採用軟體定義無線電的方式實現。
一般的情形下,軟體定義無線電採用數位訊號處理器(Digital Signal Processor)為實現平台。而為了能夠因應基地台端的大量資料量,我們改用繪圖處理器(Graphics Processing Unit)來進行軟體實現,透過「統一計算架構」(Compute Unified Device Architecture)來利用繪圖處理器之多核心具有的高度平行處理能力,並藉由分析同步演算法並配合統一計算設備架構的硬體以及軟體架構進行平行化設計,我們在繪圖處理器上實現出一個包含了初始同步、估測載波頻率飄移、計算殘餘載波頻率及取樣時脈飄移的追蹤迴路、補償載波頻率飄移和取樣時脈飄移等機制之同步器。最後再進一步經由一連串軟體開發流程來使此同步器能達到基地台端同步器的即時運算與多用戶容量需求。 | zh_TW |
dc.description.abstract | In 2008, ZTE in China has launched the ZXGW B8036 SDR (Software-Defined Radio) base-station, the world’s first pre-commercial SDR base-station. The concept of SDR is a solution for enabling one set of hardware to support multi-standards. Because of the reconfigurability, SDR can cut out the high cost of the conventional way by using one ASIC (Application-Specific Integrated Circuit) chip per system in a single device. In addition, SDR has the adaptability and flexibility for future modifications, and even upgrades to new standards. In this Thesis, we propose a synchronizer architecture for base-station according to IEEE 802.16d OFDM specifications, and implement it through SDR.
Conventionally, SDR uses DSPs (Digital Signal Processor) as platforms. In order to be able to process the massive data at a base-station, we implement our work on GPU (Graphics Processing Unit). By using CUDA (Compute Unified Device Architecture), we can utilize the highly-efficient parallel-processing power of GPU’s many-core architecture. Through the analysis of the synchronization algorithms and the hardware architecture and the software hierarchy of CUDA, we implement a synchronizer containing initial synchronization, CFO (Carrier Frequency Offset) estimation, residual CFO and SCO (Sampling Clock Offset) estimations and compensations of CFO and SCO. Finally, we apply a design flow to enable the synchronizer to meet the requirements of real-time processing and multiuser capacity. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T02:46:12Z (GMT). No. of bitstreams: 1 ntu-100-R98943097-1.pdf: 2779196 bytes, checksum: 946540ee76bfdee0ab9a528bdf89da0f (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES vii LIST OF TABLES ix CHAPTER 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Introduction to IEEE 802.16d Networks 2 1.3 Introduction to GPU and CUDA 5 1.4 Thesis Organization 7 CHAPTER 2 COMPUTE UNIFIED DEVICE ARCHITECTURE 9 2.1 Software Programming Models 9 2.1.1 Execution Model 9 2.1.2 Thread Hierarchy 11 2.1.3 Memory Hierarchy 12 2.2 Hardware Architecture 14 2.2.1 GPU Hardware Architecture Introduction 14 2.2.2 Thread Scheduling on GPU 17 2.3 CUDA Programming Guides 19 2.3.1 C Extensions 19 2.3.2 Programming Guides 21 CHAPTER 3 SYNCHRONIZATION ERRORS AND COMPENSATION 23 3.1 Introduction of Orthogonal Frequency Division Multiplexing 23 3.2 OFDM System of WiMAX 25 3.2.1 System Parameters and Symbol Format 25 3.2.2 Frame Structure 29 3.3 Synchronization Errors 31 3.3.1 Carrier Frequency Offset 31 3.3.2 Sampling Clock Offset 32 3.4 Estimation and Compensation of Synchronization Errors 33 3.4.1 Coarse Symbol Boundary Detection and Fractional CFO Estimation 34 3.4.2 Fine Symbol Boundary Detection and Integer CFO Estimation 36 3.4.3 Estimation of Residual CFO and SCO 37 3.4.4 Compensation of CFO 39 3.4.5 Compensation of SCO 40 CHAPTER 4 SOFTWARE IMPLEMENTATION ON GPU 41 4.1 System Scenario 41 4.1.1 Introduction and Requirements of System Scenario 41 4.1.2 Design Flow 43 4.2 Algorithm Implementing and Parallelizing on GPU 44 4.2.1 Scenario Analysis and Program Architecture 45 4.2.2 Parallelizing Fractional and Integer CFO Estimations 45 4.2.3 Parallelizing CFO and SCO Compensations 47 4.2.4 Parallelizing CP Removal and Post-FFT 49 4.2.5 Parallelizing Residual CFO and SCO Estimations 50 4.3 Optimizations 51 4.3.1 I/O Traffic Saturation and Pipelining 51 4.2.2 Other Optimizations 53 CHAPTER 5 EXPERIMENT RESULTS AND ANALYSIS 55 5.1 Initial Results after Parallelizing 55 5.2 Results after Optimizations 59 5.3 Results after Pipelining 60 5.4 Overall Results 62 CHAPTER 6 CONCLUSION 67 REFERENCE 69 | |
dc.language.iso | en | |
dc.title | 實現於繪圖處理器軟體之WiMAX基地台端同步器 | zh_TW |
dc.title | GPU Software Implementation of a Synchronizer for Fixed WiMAX Base-Station | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 闕志達(Tzi-Dar Chiueh),林伯星(Bor-Shing Lin) | |
dc.subject.keyword | 軟體定義無線電,802.16d,同步器,繪圖處理器,統一計算架構, | zh_TW |
dc.subject.keyword | Software-Defined Radio,802.16d,Fixed WiMAX,Synchronizer,GPU,CUDA, | en |
dc.relation.page | 70 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-08-01 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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