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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31253完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Yen-Ting Liu | en |
| dc.contributor.author | 劉彥廷 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:38:36Z | - |
| dc.date.available | 2009-01-24 | |
| dc.date.copyright | 2007-01-24 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-01-14 | |
| dc.identifier.citation | [1] Behzad Razavi, “Design of Integrated Circuits for Optical Communications,” McGRAW-HILL, International Edition 2003
[2]Agilent Technologies, “10 Gigabit Ethernet and the XAUI Interface,” http:/cp.literature.agilent.com/litweb/pdf/5988-5509EN.pdf [3]IEEE P802.3ae 10Gb/s Ethernet Task Force http://grouper.ieee.org/groups/802/3/ae/ [4]A. Fiedler, R. Mactaggart, J. Weich, S. Krishnan, 'A 1.0625 Gbps transceiver with 2×-oversampling and transmit signal pre-emphasis,' in IEEE ISSCC Dig. Tech. Papers, Feb. 1997, pp. 238-239. [5]Y. Moon, D.-K. Jeong, and G. Ahn, “A 0.6-2.5 Gbaud CMOS tracked 3× oversampling transceiver with dead-zone phase detection for robust clock/data recovery,” IEEE J. Solid-State Circuits, vol. 36, NO.12, pp. 1974-1983, Dec. 2001. [6]Chih-Kong Ken Yang, Ramin Farjad-Rad, and Horowitz, M.A., “A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling,” IEEE J. Solid-State Circuits, vol. 33, NO.5, pp. 713-722, May 1998. [7]van Ierssel, M., Sheikholeslami, A., and Tamura, H.; Walker, W.W., “A 3.2Gb/s semi-blind-oversampling CDR,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 1304-1313. [8]M. Lee, Y. Shin, S. Kim, D. k. Jeong, G. Kim, B. Kim, and V. Da Costa, '1.04 GB/s low EMI digital video interface system using small swing serial link technique, ' IEEE J. Solid-State Circuits, vol. 33, NO. 5, pp. 816-823, May 1998. [9]J. Kim, and D.-K. Jeong, “Multi-gigabit-rate clock and data recovery based on blind oversampling,” IEEE Comm. Magazine, pp. 68-74, Dec., 2003. [10]Jafar Savoj and Behzad Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” IEEE J. Solid-State Circuits, vol. 36, NO.5, pp. 761-768, May. 2001. [11]Rong-Jyi Yang, Shang-Ping Chen, and Shen-Iuan Liu, 'A 3.125Gbps clock and data recovery circuit for the 10Gbase-LX4 Ethernet', IEEE J. Solid-State Circuits, vol. 39, NO.8, pp. 1356-1360, Aug. 2004. [12]J. Lee and B. Kim, ”A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. Solid-State Circuits, vol. 35, NO.8, pp. 1137-1145, Aug. 2000. [13]Myung-Woon Hwang, John-Tae Hwang, Gyu-Hyeong Cho, “Design of high speed CMOS prescalar,” The Second IEEE Asia Conference on ASICs, pp. 87-90, Aug. 2000. [14]http://cache.national.com/ds/LM/LM117.pdf [15]Jri Lee and Behzad Razavi, 'A 40-Gb/s clock and data recovery circuit in 0.18-mm CMOS Technology,' IEEE J. Solid-State Circuits, vol. 38, NO.12, pp. 2181-2190, Dec. 2003. [16]Rong-Jyi Yang and Shen-Iuan Liu, 'A fully integrated 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector', IEICE Trans. on Electronics, vol.E88-C, pp. 1726-1730, Aug. 2005 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31253 | - |
| dc.description.abstract | 時脈資料回復電路在有線通訊系統中扮演一個重要的角色，將經過長距離傳輸後具有雜訊和抖動的資料回復成乾淨的資料以利下一級電路的使用。而電路的實現通常是使用鎖相迴路的方式達成目的，在實現架構上也有多種的選擇。本論文將分為兩個主要部份來介紹，在進入主題之前，會介紹一些時脈資料回復電路在不同架構上的實現方式。
在第一部份的3.125Gb/s半速率時脈資料回復電路中，利用一個源極追隨器增加環振盪器的線性可調範圍，使用DQFD可避免在頻率鎖定後仍然產生輸出影響充電泵造成頻率漂移。量測的結果，在1.8伏特電源供應下消耗108.4毫瓦，輸入231-1的PRBS得到時脈的峰對峰抖動和方均根抖動分別為55.6微微秒和6.61微微秒。 在本論文的第二部份，把時脈資料回復電路換成1/4速率的架構，提供兩個相差2個位元時間的時脈讓延遲鍊頻率偵測器對振盪器頻帶做選擇，選頻完成後數位電路會關掉偵測器主體以達省電功能。量測的結果，在1.8伏特電源供應下消耗103.74毫瓦，輸入2.48832Gb/s 27-1的PRBS得到時脈的峰對峰抖動和方均根抖動分別為31.1微微秒和5.06微微秒。 | zh_TW |
| dc.description.abstract | A clock and data recovery circuit plays an important role in wireline communication systems. It serves to recover the data with jitters and noises passed through long-distance transmission. The implementation is usually achieved by a phase-locked loop (PLL), and there are many choices for the implementation architectures. This work is divided into two parts: a half-rate CDR and a quarter-rate CDR with the delay-chain frequency detector will be reported.
A 3.125Gb/s half-rate clock and data recovery circuit is implemented first. A source follower is utilized to increase the linear tuning range of the ring oscillator. Half-rate digital quadricorrelator frequency detector (DQFD) is used to avoid the frequency drift due to the active charge pump when loop is locked. The measured power consumption is 108.4mW under a 1.8V supply voltage. The measured clock peak-peak jitter and rms jitter under 231-1 PRBS are 55.6ps and 6.61ps, respectively. In the second part, the CDR is changed into the 1/4-rate architecture. Two clocks with two bit times difference are applied to the delay-chain frequency detector to choose the operating band of the VCO. After completing the operation of frequency selection, digital control circuits will turn off the core of the frequency detector. The measured power consumption is 103.7mW under a 1.8-V supply voltage. The measured clock peak-peak jitter and rms jitter with 2.4883Gb/s 27-1 PRBS are 31.1ps and 5.06ps, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:38:36Z (GMT). No. of bitstreams: 1 ntu-96-R93943098-1.pdf: 5110179 bytes, checksum: fb447711165143d1229127ac4b840872 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Why CDR 1 1.2 Specifications 2 1.2.1 Jitter Performance 2 1.2.2 Transmit Data Eye Diagram 5 Chapter 2 Categories of Clock and Data Recovery Circuits 7 2.1 CDR Topologies based on VCO Operation Rate 7 2.3.1 Full-rate 7 2.3.2 Half-Rate 7 2.3.3 Quarter-Rate 9 2.2 Different PD Implementations 10 2.2.1 Linaer PD 11 2.2.2 Bang-Bang PDHalf-Rate 12 2.2.3 Oversampling PD 13 2.2.4 Blindly-Oversampling PD 15 2.3 Loop Parameters Consideration 17 2.3.1 Closed-Loop Jitter by VCO 17 2.3.2 Jitter Tolerance 19 Chapter 3 A Half-Rate 3.125Gb/s CDR Using Digitally-Controlled Ring Oscillator 21 3.1 System Architecture 21 3.2 Building Blocks 22 3.2.1 Half-Rate Linear Phase Detector 22 3.2.2 Half-Rate Digital Quadricorrelator Frequency Detector 24 3.2.3 Ring Oscillator 27 3.2.4 Charge Pump 30 3.3 Simulation Results 31 3.3.1 Behavioral Simulation 31 3.3.2 Circuit-Level Simulation 33 3.4 Experimental Results 36 3.4.1 Testing Environment Setup 36 3.4.2 PCB Manufacturing 37 3.4.3 Measurement Results 40 3.4.4 Reviews 40 3.5 Performance Summary 44 3.6 Conclusions 45 Chapter 4 A Quarter-Rate 3.125Gb/s CDR Using Delay-Chain Frequency Detector 49 4.1 System Architecture 49 4.2 Building Blocks 50 4.2.1 Quarter-Rate Binary Phase Detector 50 4.2.2 Ring Oscillator 51 4.2.3 Delay-Chain Frequency Detector 52 4.2.3.1 Operation Principle 53 4.2.3.2 Implementation 55 4.3 Simulation Results 59 4.4 Experimental Results 62 4.4.1 Testing Environment Setup 62 4.4.2 PCB Manufacturing 63 4.4.3 Measurement Results 65 4.5 Performance Summary 69 4.6 Conclusions 70 Chapter 5 Conclusions and Future Work 71 5.1 Conclusions 71 5.2 Future Work 71 Bibliography 73 | |
| dc.language.iso | en | |
| dc.subject | 時脈資料回復電路 | zh_TW |
| dc.subject | clock and data recovery circuit | en |
| dc.title | 使用延遲鍊頻率偵測器之3.125Gb/s時脈資料回復電路之設計與實現 | zh_TW |
| dc.title | Design and Implementation of 3.125Gb/s Clock and Data Recovery Circuit Using Delay-Chain Frequency Detector | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曾英哲(Ying-Che Tseng),呂良鴻(Liang-Hung Lu),陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 時脈資料回復電路, | zh_TW |
| dc.subject.keyword | clock and data recovery circuit, | en |
| dc.relation.page | 74 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-01-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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