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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳怡然 | |
| dc.contributor.author | Feng-Kuan Su | en |
| dc.contributor.author | 蘇峰寬 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:35:36Z | - |
| dc.date.available | 2010-01-24 | |
| dc.date.copyright | 2007-01-24 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-01-19 | |
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Giulio, “Genetic Optimization of Charge-Pump PLL Parameters,” The 2002 45th Midwest Symposium on Circuits and Systems, Vol.1, pp.I555-I558, Aug. 2002. [19] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” Cambridge University, 2002. [20] Maneatis, J.G., “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, Volume 31, Issue 11, Nov. 1996 Page(s):1723 – 1732 [21] R. A. Baki and N. El-Gamal, “A New CMOS Charge Pump for Low-Voltage(1V) High-Speed PLL Application,” Proceesings of the 2003 International Symposium on Circuits and System, Vol. 1, pp.I657-660, May 2003. [22] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp.521-525, June 2001. [23] T. J. Yamaguchi, M. Soma and M. Ishida, “Extraction of Instantaneous and RMS Sinusoidal Jitter Using an Analytic Signal Method,” IEEE Transaction on Circuit and Systems, Vol. 50, No. 6, June 2003. [24] T. J. Yamaguchi, M. Soma and M. Ishida, “Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method,” The 18th IEEE VLSI Test Symposium, pp.392-402, May 2000. [25] Y. A. Eken and J. P. Uyemura, “A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18--μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, pp.230-233, January 2004. [26] S. Levantino, C. Samori and A. Bonfanti, “Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Upconversion,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp.1003-1011, August 2002. [27] Magoon, R.; Molnar, A.; “RF local oscillator path for GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 8, pp.23-26, June 2002. [28] S.C. Tseng, C.C. Meng and W.Y. Chen, “SSH and SHH GaInP=GaAs HBT divide-by-3 prescalers with true 50% duty cycle,” ELECTRONICS LETTERS , Vol. 42, No. 14, 6th July 2006. [29] Antoine, P.; Bauser, P.; Beaulaton, H.; Buchholz, M.; Carey, D.; Cassagnes, T.; Chan, T.K.; Colomines, S.; Hurley, F.; Jobling, D.; Kearney, N.; Murphy, A.; Rock, J.; Salle, D.; Tu, C.-T.; “A direct-conversion receiver for DVB-H,” IEEE Journal of Solid-State Circuits, Vol. 1, No. 23, pp.426-427, Feb 2005. [30] Vassiliou, I.; Vavelidis, K.; Bouras, S.; Kavadias, S.; Kokolakis, Y.; Kamoulakos, G.; Kyranas, A.; Kapnistis, C.; Haralabidis, N.; “A 0.18/spl mu/m CMOS Dual-Band Direct-Conversion DVB-H Receiver,” Solid-State Circuits, pp. 2494-2503, Feb 2006. [31] Young-jin Kim; Jae-wan Kim; Parkhomenko, V.N.; Donghyun Baek; Jae-heon Lee; Eun-yung Sung; Ilku Nam; Byeong-ha Park; “A Multi-Band Multi-Mode CMOS DirectConversion DVB-H Tuner,” Solid-State Circuits, pp. 2504-2513, Feb 2006. [32] Womac, M.; Deiss, A.; Davis, T.; Spencer, R.; Abesingha, B.; Hisayasu, P.; “Dual-band Single-Ended-Input Direct-Conversion DVB-H Receiver,” Solid-State Circuits, pp. 2514-2523, Feb 2006. [33] Marutani, M.; Anbutsu, H.; Kondo, M.; Shirai, N.; Yamazaki, H.; Watanabe, Y.; “An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners,” Solid-State Circuits, pp. 681-690, Feb 2006. [34] H. O. Johansson, “A Simple Precharged CMOS Phase Frequency Detector,” 98 IEEE Journal of Solid-State Circuits, Vol. 33, No. 2, pp.295-299, Feb. 1998. [35] B. Chang, J. Park, and W. Kim “A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop,” IEEE J. Solid-State Circuits, vol. 31, no 5, pp. 749-752, May 1996. [36] 沈致賢, “Design and Implementation of Voltage Control Oscillator,” GIEE, National Taiwan University, Taipei, Taiwan, 2003. [37] Ye-Ming Li and J. Alvin Connelly, “Modeling A Resonant LC Tank Circuit Embedded in A VCO,” IEEE ISCAS, Proceedings, vol. 3, pp. 173-176, May 2002. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31203 | - |
| dc.description.abstract | 本論文設計一個低電壓、低成本、寬頻且快速鎖定，且可應用在DVB-H UHF頻段的三階頻率合成器，該頻率合成器被使用在偶次諧波混波器的直接降頻接收器（Direct down-conversion Receiver）上。頻率合成器提供675M∼1275MHz的頻率輸出，在輸出端加入除三電路之後產生225M∼425MHz，這訊號可作為Even-Harmonic Mixer本地震盪的訊號。
以精簡DFF組成的相位頻率檢測器和差動操作的電荷幫浦來提升電路的操作速度，可提高輸入參考頻率的大小，減少系統的鎖定時間；利用四位元的控制訊號來切換MIM電容陣列，可改變電壓控制震盪器的中心頻率，增加電壓控制震盪器的輸出範圍；由控制可程式化的除頻器，可讓我們獲得想要使用的輸出頻率 電路設計採用tsmc 0.18um CMOS Mixed/RF製程，操作電壓為1V。輸入的參考訊號為48MHz，再透過輸入的除頻器決定頻寬大小為8MHz或6MHz，因此再輸出端可得到跳頻為6MHz或8MHz兩種頻寬的輸出。有675M∼1275MHz和225M∼425MHz兩種輸出訊號可以使用，鎖定時間小於20us，功率消耗小於13mW，相位雜訊在1.45MHz偏移時小於-126.28dBc/Hz，晶片大小為1.0605mm2。 | zh_TW |
| dc.description.abstract | A low cost, low voltage, wide-bandwidth and fast-locking of 3rd frequency synthesizer is designed. The single voltage-controlled oscillator (VCO) covered the frequency from 675 MHz to 1275 MHz. The divide-by-three prescaler is integrated on chip to provide the I/Q signals from 225 MHz to 425 MHz, and the outputs can be used as the LO of the UHF TV even-harmonic direct down-conversion.
The differential control help to shorten the response time of the charge pump. And, the propagation delay of the D flip-flops is reduced to facilitate high reference clock of phase frequency detector. The dead zone issue does not exist in this design. The frequency divider architecture is pulse-swallow counter. By controlled program counter and swallow counter, frequency divider operation range is between 2 to 192. The frequency synthesizer was implemented in TSMC CMOS 0.18um 1P6M technology. The die size is 1.05×1.01 mm2. The supply voltage of the frequency synthesizer is 1V and the power consumption is 13 mW. The measured phase noise is -127.28 dBc/Hz at 1.45MHz offset from carrier. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:35:36Z (GMT). No. of bitstreams: 1 ntu-96-R92943064-1.pdf: 2775353 bytes, checksum: e5e4cfcab0e516dfd7ddb844952367fc (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 目錄
口試委員會審定書………………………………………………………………….....I 誌謝 III 中文摘要 V 英文摘要 VII 目錄 IX 圖目錄 XI 表目錄 XV 第一章 2 緒論 2 1.1 研究背景與動機 2 1.2 數位電視廣播系統簡介[1] 4 1.2.1 類比電視比較 4 1.2.2 數位電視的規格 6 1.2.3 行動數位電視 7 1.3 頻率合成器的種類與架構 10 1.3.1 數位式頻率合成器（Digital Synthesizer） 10 1.3.2 直接式頻率合成器（Direct Synthesizer） 11 1.3.3 鎖相迴路的頻率合成器（PLL-Based Synthesizer） 11 1.4 數位電視調節器的架構[5] 13 1.4.1 單轉換中頻輸出 13 1.4.2 雙轉換中頻輸出 14 1.4.3 單轉換低中頻輸出 14 1.4.4 雙轉換低中頻輸出 15 1.4.5 雙轉換零中頻輸出 16 1.4.6 單轉換零中頻輸出 17 1.5 論文簡介 18 第二章 20 鎖相迴路的基本理論 20 2.1 鎖相迴路的類型 20 2.1.1 類比型鎖相迴路 20 2.1.2 混合信號型鎖相迴路 21 2.1.3 全數位型鎖相迴路 21 2.1.4 數位信號處理型鎖相迴路 22 2.2 鎖相迴路的電路架構 23 2.2.1 相位/頻率檢測器 24 2.2.2 電荷幫浦 28 2.2.3 電壓控制震盪器 29 2.2.4 除頻器 34 2.2.5 迴路濾波器 36 2.3 鎖相迴路的線性模型 38 2.3.1 一階鎖相迴路 39 2.3.2 二階鎖相迴路 40 2.3.3 三階鎖相迴路 42 2.3.4 四階鎖相迴路 45 2.4 鎖相迴路的效能指標 47 2.4.1 相位雜訊的定義及影響 47 2.4.2 鎖相迴路相位雜訊來源分析 48 2.4.3 Sidebands（Spurs） 50 第三章 52 電路設計 52 3.1 電視調節器系統規格與架構 52 3.2 寬頻CMOS頻率合成器的規格 54 3.3 行為模擬 56 3.4 設計原理與製作流程 58 3.4.1 相位頻率檢測器的設計與模擬 59 3.4.2 電荷幫浦的設計與模擬 63 3.4.3 電壓控制震盪器的設計與模擬 65 3.4.4 除頻器的設計與模擬 73 3.4.5 類比除三電路的設計與模擬 78 3.4.6 頻率合成器的設計與模擬 81 第四章 83 下線與量測 83 4.1 佈局與驗證 83 4.1.1 量測儀器及PCB版佈局 85 4.2 IC1量測結果 87 4.3 IC2量測結果 91 第五章 93 結論與發展方向 93 5.1 結論 93 5.2 發展方向 93 | |
| dc.language.iso | zh-TW | |
| dc.title | 一伏寬頻頻率合成器 | zh_TW |
| dc.title | 1V Wideband Frequency Synthesizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曹恆偉,黃崇禧,陳冠達 | |
| dc.subject.keyword | 數位電視,頻率合成器, | zh_TW |
| dc.subject.keyword | DTV,Synthesizer,DVB-H, | en |
| dc.relation.page | 98 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-01-22 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-96-1.pdf 目前未授權公開取用 | 2.71 MB | Adobe PDF |
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