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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31108完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Feng-Neng Tsai | en |
| dc.contributor.author | 蔡豐能 | zh_TW |
| dc.date.accessioned | 2021-06-13T02:30:13Z | - |
| dc.date.available | 2008-02-02 | |
| dc.date.copyright | 2007-02-02 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-01-25 | |
| dc.identifier.citation | 參考文獻
[1] W. Humann, “Compensation of transmission line loss for gbit/s test on ATEs,” IEEE International Test Conf., pp.430-437, Jan. 2002. [2] J. D. Geest, S. Sercu, and J. Nadolny, “ How to make optimal use of signal conditioning in 40 gb/s copper interconnects,” DesignCon2003, High-Performance System Design Conf., Jan. 2003. [3] W. T. Beyene, N. Cheng, J. Feng, H. Shi, D. Oh, and C. Yuan, “Performance analysis of multi-gigahertz parallel bus with transmit pre-emphasis equalization,” IEEE MTT-S international microwave symposium digest ISSN 0149-645X, 2005, vol. 4, pp. 1849-1852 [4] K. Yamagishi and A. Saito, “Methods of eye-pattern window improvement using Reflections caused by impedance mismatch post-emphasis Technique,” IEEE Electrical performance electric packaging, pp.209-212, Oct. 2005.pp.209-212 [5] K. J. Han, H. Takeuchi, E. Engin and M. Swaminathan, “Eye-pattern improvement for design of high-speed differential links using passive equalization,” Topical meeting on electrical performance of electronic packaging, 2006 [6] D. M. Pozar, “Microwave engineering, 2nd Ed.,” John Wiley & Sons, Inc., 1998, Ch. 2 [7] A. Semlyen and M. H. Abdel-Rahman, “Transmission line modeling by rational transfer functions,” IEEE Trans. Power App. Syst., vol. PAS-101, pp. 389-395, Sept. 1982. [8] S. H. Hall, Garrett W. Hall and James A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc., 2000, pp.74-88. [9] Howard Johnson and Martin Graham, High-Speed Signal Propagation, Prentice Hall, Inc., 2003, p.94. [10] H. Yue, K. L. Virga, John L. Prince, “Dielectric constant and loss tangent measurement using a stripline fixture,” IEEE Trans. Comp. Package, , Nov. 1998, pp.441-446. [11] G. Breed, “Analyzing signals using the eye diagram,” High Frequency Electronics, Nov. 2005. [12] R. Vezina, “PCIe 2.0 5ghz signaling tutorial, ” PCIe2:5ghz signaling tutorial Intel Inc. [13] C. R. Paul, Introduction to Electromagnetic Compatibility (second edition), Wiley, Inc., Ch4. [14] S. H. Hall, Garrett W. Hall and J. A. McCall, High-Speed Digital System Design, John Wiley & Sons, Inc., 2000, p.15. [15] ADS(Advanced Design System) tutorial , Agilent technologies corporation. [16] R. B. Wu, Time-domain simulation for transmission lines, Research project under grant NSC-80-0404-E002-36, 1990. [17] W. Fan, A. Lu, L. L. Wai, B. K. Lok, “Mixed-mode s-parameter characterization of differential structures,” IEEE Electronics packaging technology conf. pp.533-537,2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31108 | - |
| dc.description.abstract | 本文主要是針對阻抗不匹配反射來改善眼圖作探討。信號在高速傳輸時，主要的損耗是來自傳輸線隨頻率增高所帶來的高損耗，為了避免因嚴重的損耗而使電壓波型失真，甚至造成邏輯位準的誤判而使電路誤動作，所以就利用高阻抗元件所產生的反射量疊加來改善接收端的波型信號完整度。
此外，吾人以電感和高阻抗傳輸線長做為高阻抗元件，並對其做了詳盡探討和分析，依據其反射量疊加原理推導出一套準確的補償方法。當吾人只要知道傳輸線的損耗時，就可快速且準確地知道欲加入的補償元件，這樣不僅可大幅改善信號的完整度，也可節省模擬與設計的時間。 | zh_TW |
| dc.description.abstract | The thesis focuses on eye diagram improvement using reflections caused by impedance mismatch for lossy lines. When signal transmits at high speed, the loss that comes from the transmission line increases. In order to avoid the resultant voltage waveform distortion the misjudgment of digital signal, and even system failure, utilizes the superposition of reflection by high impedance line to improve the signal integrity of the wave form at receiver.
In addition, this study utilizes an inductor or a high impedance line as the high impedance component and investigates its performance. A set of design rule has been derived for inductance value and length of high impedance transmission line. Given the frequency dependence of the transmission line loss, one can find out accurately the desired compensation. This may not only improve the signal integrity, but also save the time of simulation and design. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T02:30:13Z (GMT). No. of bitstreams: 1 ntu-96-J93921013-1.pdf: 5529480 bytes, checksum: a4b5ce5c290ecab95fd55d01ef51f666 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | 目 錄
第一章 簡介.............................................1 1.1 研究動機..........................................1 1.2 文獻回顧與探討....................................3 1.3 章節概要..........................................3 1.4 成果貢獻..........................................4 第二章 有損傳輸線理論與PCI Express規格說明..............5 2.1 有損傳輸線理論....................................5 2.1.1 傳輸線上的電波傳播.............................5 2.1.2 金屬損耗與介質損耗.............................8 2.2 PCI Express規格與眼圖規範.........................14 第三章 電感反射補償.....................................18 3.1 單根傳輸線最佳化電感補償..........................18 3.1.1 理論說明.......................................18 3.1.2 最佳化電感設計.................................24 3.1.3 模擬分析.......................................32 3.2 差模傳輸線最佳化電感補償..........................37 3.2.1 最佳化電感設計流程.............................37 3.2.2 模擬分析.......................................42 3.3 輸入信號與傳輸線頻率響應的關係....................46 3.3.1 輸入信號頻譜對眼圖的分析.......................46 3.3.2 高速數位信號頻譜落在過度補償的 分析............51 3.4 補償電路的適用範圍................................53 第四章 高阻抗傳輸線反射補償.............................56 4.1 理論說明..........................................56 4.2 最佳化高阻抗線長設計流程..........................59 4.3 估算法求解........................................63 4.4 模擬分析..........................................64 第五章 實驗驗證.........................................72 5.1 量測環境建立......................................72 5.2 實驗量測..........................................74 5.2.1 單根傳輸線補償.................................74 5.2.2 差模傳輸線補償.................................78 5.2.3 高阻抗傳輸線補償...............................81 第六章 結論與未來工作...................................84 6.1 結論..............................................84 6.2 未來工作..........................................84 參考文獻................................................85 | |
| dc.language.iso | zh-TW | |
| dc.subject | 等化器 | zh_TW |
| dc.subject | 信號完整度 | zh_TW |
| dc.subject | 高阻抗補償 | zh_TW |
| dc.subject | 眼圖 | zh_TW |
| dc.subject | signal integrity | en |
| dc.subject | eye pattern | en |
| dc.subject | equalizer | en |
| dc.subject | high impedance compensation | en |
| dc.title | 利用高阻抗不匹配改善損耗線之眼圖 | zh_TW |
| dc.title | Eye-Pattern Improvement Using High Impedance Mismatch for Lossy Lines | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 吳瑞北(Ruey-Beei Wu) | |
| dc.contributor.oralexamcommittee | 吳宗霖(Tzon-Lin Wu),薛光華,林文傑 | |
| dc.subject.keyword | 眼圖,高阻抗補償,等化器,信號完整度, | zh_TW |
| dc.subject.keyword | eye pattern,high impedance compensation,equalizer,signal integrity, | en |
| dc.relation.page | 86 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-01-25 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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