使用接地防護線降低串音雜訊

Chia-Ying Chao; 趙嘉瀅

請用此 Handle URI 來引用此文件： http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31024

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.advisor	吳瑞北
dc.contributor.author	Chia-Ying Chao	en
dc.contributor.author	趙嘉瀅	zh_TW
dc.date.accessioned	2021-06-13T02:25:55Z	-
dc.date.available	2010-02-01
dc.date.copyright	2007-02-01
dc.date.issued	2007
dc.date.submitted	2007-01-28
dc.identifier.citation	參考文獻 [1] I. Novak, B. Eged, and L. Hatvani, “Measurement by vector-network analyzer and simulation of crosstalk reduction on printed circuit boards with additional center traces,” in Proc. IEEE Instrument. Measurement Technol., Irvine, CA, pp. 269–274, May 1993 [2] H. W. Johnson, High-speed digital design: a handbook of black magic, Englewood Cliffs, N.J. Prentice Hall,1993, ch5 pp.201 [3] E. Bogatin, Signal Integrity – Simplified, Prentice Hall,2003, ch10, p. 452 [4] L. Zhi, W. Qiang, and S. Changsheng, “Application of guard traces with vias in the rf pcb layout,” in Proc. IEEE Int. Symp. Electromagnetic Compat., pp. 771–774, May 2002. [5] A. Suntives, A. Khajooeizadeh, and R. Abhari, “Using via fences for crosstalk reduction in PCB circuits,” in Proc. IEEE Int. Symp. Electromagnetic Compat., pp. 34–37, Aug. 2006. [6] S. Nara and K. Koshiji, “Study of delay time characteristics of multi-layered hyper-shield meander line,” in Proc. IEEE Int. Symp. Electromagnetic Compat., pp. 760–763, Aug. 2006 [7] D. N. Ladd and G. I. Costache, “SPICE simulation used to characterize the crosstalk reduction effect of additional tracks grounded with vias on printed circuit boards,” IEEE Truns. Circuits Syst. II, vol. 39, pp. 342-347, June 1992 [8] R. B. Wu and F. L. Chao, “Flat spiral delay line design with minimum crosstalk penalty” Components, Packaging, and Manufacturing Technology, Advanced Packaging, IEEE Transactions, pp. 397 – 40, May 1996 [9] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System. Design, A Handbook of Interconnect Theory and Design Practices. Hoboken, NJ: Wiley, 2000, ch. 3, p. 48, p. 53, Appendix. C, p. 330 [10] C. R. Paul, Introduction to Electromagnetic Compatibility 2ed edition, John Wiley & Sons, 2006, ch. 3, p. 129 [11] R. B. Wu, Time-Domain Simulation for Transmission Lines, Research Project under Grant NSC-80-0404-E002-36, 1990. [12] HSPICE, SYNOPSYS Corporation. (www. synopsys.com) [13] HSPICE Signal Integrity Guide Version W-2005.03 [14] ADS 2005A, Agilent Technologies. (www.agilent.com) [15] D. M. Pozar, Microwave Engineering 3rd ed, John Wiley, 2005, ch.7, pp. 437 – 448 [16] C. L. Wang, G. H. Shiue and R. B Wu, “EBG-enhanced split power planes for wideband noise suppression”, Electrical Performance of Electronic Packaging, 2005. IEEE 14th Topical Meeting, pp.61 – 64, Oct. 2005. [17] Y. S. Sohn, J. C. Lee, H. J. Park and S. I. Cho, “Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board”, Advanced Packaging, IEEE Transactions, pp.521 – 527, Nov. 2001. [18] R. B. Wu and F. L. Chao, “Laddering wave in serpentine delay line,” IEEE Trans. Comp., Pkg., Manuf. Technol., B, vol. 18, no. 4, pp. 644–650, Nov. 1995. [19] W. D. Guo, G. H. Shiue, and R. B.Wu, 'Comparison between serpentine and flat spiral dealay lines on Tranaient Reflection/Transmission waveforms and eye diagrams', IEEE Trans. Microwave Theory Tech., vol. 54, pp. 1379-1387, April 2006. [20] C.Rostam, “Experimental investigation of PCBb guard traces on radiated EMI” in Proc. IEEE Int. Symp. Electromagnetic Compat., pp. 529–533, Aug. 2006.
dc.identifier.uri	http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/31024	-
dc.description.abstract	在高速數位電路中，微帶線間的串音(crosstalk)現象為影響信號完整度主要因素之一。為了降低耦合線間的串音，可在相互干擾的耦合微帶線間插入一列以接地連通柱(via)形成之導線結構來提供信號保護能力以防備非預期串音干擾，此結構稱之為防護線(guard trace)。然而，防護線上的接地連通柱若無適當的設計，反而會讓防護線形成另一條干擾線，使得串音問題在受擾線(victim trace)端更加嚴重。因此本文將針對加入接地防護線後，於時域上產生之串音雜訊進行估算及成因分析。並利用實驗與模擬驗證來有效設計接地防護線以降低耦合線間的串音問題。最後將防護線特性應用於電路延遲線(delay line)設計，用以改善時域反射與穿透(time-domain reflection and transmission, TDR/TDT)信號完整度及延遲時間偏差(time skew)等問題，以提供日後進行相關電路佈線，解決串音問題之設計方式。	zh_TW
dc.description.provenance	Made available in DSpace on 2021-06-13T02:25:55Z (GMT). No. of bitstreams: 1 ntu-96-J93921016-1.pdf: 10601743 bytes, checksum: 00712833f5049085a3a421c4100fc75f (MD5) Previous issue date: 2007	en
dc.description.tableofcontents	目錄第一章簡介 …………………………………………………………………… 1 1-1 研究動機 ……………………………………………………………… 1 1-2 文獻回顧與探討 ……………………………………………………… 1 1-3 章節概要 ……………………………………………………………… 2 1-4 成果貢獻 ……………………………………………………………… 3 第二章串音理論分析 ………………………………………………………… 5 2-1 串音成因與等效電路模型 …………………………………………… 5 2-2 傳輸線電感電容矩陣 ………………………………………………… 7 2-3 耦合線串音雜訊量分析與估算公式推導 …………………………… 7 2-4 耦合線間加入防護線後之串音雜訊抑制效果分析 ………………… 15 第三章利用多個接地連通柱組成之防護線架構分析 ……………………… 21 3-1 耦合線間加入由接地連通柱組成之防護線串音雜訊分析 ………… 21 3-2 連通柱擺放間距對串音抑制效果與分析 …………………………… 43 3-3 防護線線寬與連通柱結構對串音雜訊抑制效果分析 ……………… 53 3-4 不同的防護線擺放型式對串音雜訊的抑制效果分析 ……………… 57 3-5 嵌入微帶線加入防護線抑制串音雜訊效果 ………………………… 59 第四章接地防護線的應用--改善延遲線信號完整度 ……………………… 61 4-1 蛇形延遲線 TDR與TDT串音分析 …………………………………… 61 4-2 蛇形延遲線加入防護線後TDR與TDT串音分析 ……………………… 66 4-3 蛇形延遲線加入防護線後對信號完整度的改善 …………………… 69 4-4 螺旋形延遲線加入防護線後對信號完整度的改善 ………………… 78 第五章實驗驗證 ……………………………………………………………… 83 5-1 防護線接地連通柱擺放間距對串音抑制分析 ……………………… 83 5-2 蛇形延遲線加入防護線後TDR與TDT量測分析 ……………………… 90 5-3 蛇形延遲線加入防護線後眼圖量測分析 …………………………… 97 第六章結論與未來工作 ……………………………………………………… 107 6-1 結論 …………………………………………………………………… 107 6-2 未來工作 ……………………………………………………………… 108 參考文獻………………………………………………………………………… 109
dc.language.iso	zh-TW
dc.subject	防護線	zh_TW
dc.subject	串音	zh_TW
dc.subject	延遲線	zh_TW
dc.subject	crosstalk	en
dc.subject	guard trace	en
dc.subject	delay line	en
dc.title	使用接地防護線降低串音雜訊	zh_TW
dc.title	Crosstalk Noise Reduction Using Guard Trace	en
dc.type	Thesis
dc.date.schoolyear	95-1
dc.description.degree	碩士
dc.contributor.oralexamcommittee	吳宗霖,薛光華,賴明昇
dc.subject.keyword	串音,防護線,延遲線,	zh_TW
dc.subject.keyword	crosstalk,guard trace,delay line,	en
dc.relation.page	110
dc.rights.note	有償授權
dc.date.accepted	2007-01-29
dc.contributor.author-college	電機資訊學院	zh_TW
dc.contributor.author-dept	電機工程學研究所	zh_TW
顯示於系所單位：	電機工程學系

文件中的檔案：

檔案	大小	格式
ntu-96-1.pdf 未授權公開取用	10.35 MB	Adobe PDF

顯示文件簡單紀錄

系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。