高效能迴旋式低密度奇偶檢查碼解碼器之設計

Abstract

本論文提出迴轉式低密度奇偶檢查碼（LDPC-CC）解碼器之設計。因為現在的通訊技術的成長，在傳輸的過程中一定會有些不理想的效應存在，因此資料的保護是很重要的。因為區塊式低密度奇偶檢查碼（LDPC-BC）在很多不同的通道裡有很卓越的解碼功能，所以已經研究了很多年了。LDPC-CC在1999年被提出來也證明了有跟LDPC-BC相似的位元錯誤率（Bit Error Rate）。一個LDPC-CC有很好的優勢是跟LDPC-BC比較時LDPC-CC有比較少的延遲（Latency），對於LDPC-BC來說每次的解碼一定要等到一定的資料長度才可以進行解碼的工作。所以可以將LDPC-CC可以跟多輸入多輸出（Multiple Input Multiple Output）結合以達成反覆解碼（iterative decoding）。因為在硬體的架構上LDPC-CC也有一些比LDPC-BC好的特性，所以LDPC-CC的編碼器跟解碼器都比LDPC-BC好設計。在本論文裡，為了要減少解碼所需的時間，奇偶矩陣被做了一些小改變。還把存取資料的儲存庫改成Dual-port SRAM。一些基本硬體上的簡化技巧被使用在本解碼器的架構上以達成高速率跟低功率的解碼器。在最後，跟之前的解碼器比較起來我們成功的節省了50％的時間與功率。

This thesis describes the proposed design of Convolutional Low-Density Parity Check Code (LDPC-CC) decoder. Due to increasing high data transmissible rate, data protection techniques are applied to all data transmission and storage devices. Hence, LDPC block codes (LDPC-BC) have been studied over the past years due to their exceptional decoding performance on a wide variety of communication channels. Their block-counterparts, LDPC-CC codes were first proposed in 1999 and proved that those codes have similar bit-error rate (BER) performance. However, LDPC-CC codes have several advantages over LDPC-BC codes. First of all, LDPC-CC requires less latency than LDPC-BC codes for long block-length codes. Thus, it is very suitable to integrating LDPC-CC codes to iterative decoding, such as combining inner codes with outer codes in multiple-input multiple-output (MIMO) communication system, rather than integrating with LDPC-BC. In hardware architectural point of view, encoders and decoders of LDPC-CC are easier to be implemented. Based on the previous works on LDPC-CC codes, further optimization can be achieved. In order to save clock cycles, construction of a parity-check matrix is altered. For saving even more clock cycles, by changing the order of calculation sequences, dual-port SRAM is applied to our design. Some of circuit techniques, such as Wallace tree structure and linear approximation, are applied in our design in order to improve the throughput of the proposed decoder. The details of the optimizations are discussed in this thesis. In conclusion to our design, approximately 50% of clock cycles are saved comparing to [7] and 50% of the power consumption is saved compared to [8].