適用於手持式數位視訊廣播系統之快速傅利葉轉換處理器設計

Abstract

快速傅利葉轉換被廣泛運用在正交分頻多工通訊系統中，如手持式數位視訊廣播(Digital Video Broadcasting for Handheld terminals, DVB-H)系統等，作為解調變的核心。在手持式數位視訊廣播系統中需要低功率及可運算三種長度的快速傅利葉轉換處理器。 在本篇論文中，首先，我們提出一個適用於手持式數位視訊廣播系統的快速傅利葉轉換處理器，我們使用一種乒乓式(ping-pong)記憶體階層式架構，以降低存取主記憶體的次數，並可在減低最大功率的前提下，增加最少的快取記憶體，達到降低總功率消耗，並配合關閉不需使用的記憶體單元，以減低在不同傅利葉轉換長度時，不必要的記憶體功率消耗。 此外，我們設計出一個位址產生器，可提供處理三種長度傅利葉轉換計算所需存取的所有記憶單元的位址，並使用交錯(Interleaving)位址來處理主記憶體及快取記憶體會遭遇到的資料衝突。 接著，我們提出有效係數設計方法，透過共用(Sharing)及內插後共用(Interpolation-then-Sharing)係數的方式，在可損失的信號對量化雜訊比(Signal-to-Quantized-Noise Ratio, SQNR)範圍內，有效降低所需係數的面積。以此方法可有效降低我們67%的係數儲存單元面積，而在做8192點快速傅利葉運算時，SQNR只損失0.6dB。 在本論文的最後，我們使用TSMC 0.18μm製程實現了一個符合手持式數位視訊廣播系統的快速傅利葉轉換處理器的超大型積體電路（VLSI）設計實例，晶片核面積為1.886×1.886mm2，最高工作頻率為86MHz，能在805μs內運算完8192點，其功率消耗為75.31mW；在運算符合DVB-H系統所需的8192、4096、2048點傅利葉轉換的工作頻率分別為79MHz、75MHz與71MHz，功率消耗分別為67.01mW、53.16mW與39.45mW。

Fast Fourier transform (FFT) is widely adopted as the demodulation kernel in the OFDM systems such as Digital Video Broadcasting – transmission system for Handheld terminals (DVB-H) system, etc. In the DVB-H system, a low power and variable-length FFT processor is required. In this thesis, we firstly propose an FFT processor that reduces the power consumption by exploiting the ping-pong cached-memory architecture to decrease the access to main memory, and timely turning off the unused memory partitions to save energy in different sizes of the FFT. Second, we design the triple-mode address generator to handle the address mapping of all storages in the three-size of FFT computations, and it includes the interleaving method to avoid data conflicts. Then we propose two cost-efficient twiddle-factor coefficient design methods, “Sharing” and “Interpolation-then-Sharing”, to reduce the area of coefficient storages within the allowable loss of Signal-to-Quantized-Noise Ratio (SQNR). By using these methods, the area occupied by coefficient storage can be reduced by 67%. In 8192-point FFT, these modifications only cause 0.6dB loss of SQNR. In the end of this thesis, we implement our proposed FFT processor for DVB-H system with TSMC 0.18μm 1P6M CMOS technology. The core size is 1.886×1.886mm2. The minimum latency to operate 8192-point FFT is 805μs with 86MHz clock rate. And the power consumption is 75.51mW. For DVB-H system, it processes the 8192, 4096, and 2048-point FFT with clock rates of 79MHz, 75MHz, and 71MHz, and consumes of 67.01mW, 53.16mW, and 39.45mW, respectively.