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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30067完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆(Fei-pei Lai) | |
| dc.contributor.author | Min-Xuan Huang | en |
| dc.contributor.author | 黃敏軒 | zh_TW |
| dc.date.accessioned | 2021-06-13T01:34:03Z | - |
| dc.date.available | 2007-07-30 | |
| dc.date.copyright | 2007-07-30 | |
| dc.date.issued | 2007 | |
| dc.date.submitted | 2007-07-16 | |
| dc.identifier.citation | [1] P. Berman, L. Gravano, J. Sanz, and G. Pifarre, 'Adaptive Deadlock- and Livelock-Free Routing with All Minimal Paths in Torus Networks,' Proc. Fourth ACM Symp. Parallel Algorithms and Architectures, June 1992.
[2] C.J. Glass and L.M. Ni, 'Adaptive Routing in Mesh-Connected Networks,' Proc. 1992 Int'l Conf. Distributed Computing Systems, pp. 12-19, 1992. [3] Glass C,Ni L.The Turn Model for Adaptive Routing[J].Journal of ACM,1994,41. [4] Duato J. A new theory of deadlock-free adaptive routing in wormhole networks[J]. IEEE Transactions Parallel and Distributed Systems. 1993,54(12): 1320-1331. [5] R. Boppana and S. Chalasani, A comparison of adaptive wormhole routing algorithms, Proceedings of International Symposium on Computer Architecture, 1993. [6] Duato J. A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks. IEEE Trans. On Parallel and Distributed Systems, 1995,6(10):1055∼1067. [7] Chiu G.The Odd-even Turn Model for Adaptive Routing[J].IEEE Trans on Parallel and Distributed Systems,2000,11(7):729-738. [8] P. Guerrier, A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnections,” Proc. Design and Test in Europe (DATE), pp. 250-256, Mar. 2000. [9] S. Kumar et al., “A Network on Chip Architecture and Design Methodology,” in IEEE Proc. Int’l Symp. VLSI (ISVLSI), pp. 117-112, 2002. [10] .Evain, J-Ph.Diguet, D.Houzet, µSpider: A CAD Tool for Efficient NoC Design, IEEE NORCHIP 2004, Oslo, NORWAY, Nov. 8-9, 2004. [11] Jingcao Hu, Marculescu R., “Application-specific buffer space allocation for networks-on-chip router design,” ICCAD-2004, pp. 354 – 361, 7-11 Nov. 2004. [12] J. Hu and R. Marculescu, “DyAD - Smart routing for networks-on-chip,” DAC, pp. 260-263, USA, 2004. [13] K. Srinivasan, K. S. Chatha, and G. Konjevod, 'Linear programming based techniques for synthesis of network-on-chip architectures,' in Proc. Int. Conf. Comput. Des., 2004, pp. 422-429. 13 [14] D. Bertozzi et al., “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Trans. Parallel Distrib. Syst.,vol. 16, no. 2, pp. 113–129, Feb. 2005. [15] EE • Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng: Communication latency aware low power NoC synthesis. DAC 2006: 574-579. [16] EE • Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi: A concurrent testing method for NoC switches. DATE 2006: 1171-1176. [17] EE • Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Mary Jane Irwin: Reducing NoC energy consumption through compiler-directed channel voltage scaling. PLDI 2006: 193-203. [18] EE • Ümit Y. Ogras, Radu Marculescu: Prediction-based flow control for network-on-chip traffic. DAC 2006: 839-844. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/30067 | - |
| dc.description.abstract | 我們提出和評估一個新穎的路徑技術，這個技術結合了決定行演算法和完全適應型演算法。我採用了XY路徑演算法和奇偶數轉向演算法的優點。更準確的說法，是我們展望了一個可以明智而審慎地在XY路徑演算法和奇偶數轉向演算法轉換的新技術，而這樣的轉換是根據網路的壅塞情況來決定的。在模擬的結果中，可以見到所提出的動態路徑演算法結合XY路徑演算法和奇偶數轉向演算法的效能在和純粹的XY路徑演算法和奇偶數轉向演算法，而這樣的模擬是根據不同的交通型態下進行。因此，一個標準路由器以動態路徑演算法結合XY路徑演算法和奇偶數轉向演算法為主被設計和評估。相較於純粹的適應型演算法來說，實做一個動態路徑演算法結合XY路徑演算法和奇偶數轉向演算法的酬載可以被忽略的。其實，在兩者的相對比較下，奇偶數轉向演算法的酬載是動態路徑演算法結合XY路徑演算法和奇偶數轉向演算法的0.4%。然而，動態路徑演算法結合XY路徑演算法和奇偶數轉向演算法的性能固然地比XY路徑演算法和奇偶數轉向演算法還要好。而其中，動態路徑演算法的性能可以比奇偶數轉向演算法好上13.1%。 | zh_TW |
| dc.description.abstract | We present and evaluate a novel routing scheme which combines the deterministic routing algorithm and the full adaptive routing algorithm. We combine the advantages of both xy routing algorithm and odd-even turn model. More precisely, we envision a new routing technique which judiciously switches between deterministic and adaptive routing based on the network’s congestion conditions. The simulation results show the effectiveness of the Dynamic routing algorithm combining the deterministic and adaptive model by comparing it with pure xy routing algorithm and odd-even turn model under different traffic patterns. Moreover, a prototype router based on the Dynamic routing algorithm combining the deterministic and adaptive model has been designed and evaluated. Compared to purely adaptive routers, the overhead of implementing Dynamic routing algorithm combining the deterministic and adaptive model is negligible. The overhead of the odd-even turn model is 0.4% higher compared to the overhead of the dynamic routing algorithm. However, the performance is consistently better than the one of the xy routing and the one of the odd-even turn model. The performance is 13.1% better compared to the odd-even turn model. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T01:34:03Z (GMT). No. of bitstreams: 1 ntu-96-R94922156-1.pdf: 624777 bytes, checksum: ed44cae271e3214c47b59fcfff9604e4 (MD5) Previous issue date: 2007 | en |
| dc.description.tableofcontents | Abstract---------------------------------------------- 9
CHAPTER 1---------------------------------------------10 Introduction------------------------------------------10 1.1 Concept of the NOC--------------------------------10 1.2 Basic Architecture of the NOC---------------------11 1.3 Profit of the Networks-on-Chip--------------------12 CHAPTER 2 ---------------------------------------------14 Routing on Networks-on-Chip---------------------------14 2.1 Network Topology----------------------------------14 2.2 Related Work--------------------------------------20 2.3 Problems on Routing Algorithm---------------------21 2.3.1 Deadlock----------------------------------------21 2.3.2 Livelock----------------------------------------21 2.3.3 Deadlock-Free Problem---------------------------22 2.4 Concept of the XY Routing Algorithm---------------25 2.5 Concept of the Odd-Even Turn Model----------------27 2.6 Network Flow Control------------------------------29 2.6.1 Store-and-Forward Routing-----------------------29 2.6.2 Virtual Cut-Through Routing---------------------29 2.6.3 Wormhole Routing--------------------------------30 CHPATER 3---------------------------------------------31 The Architecture of Dynamic Routing Algorithm---------31 3.1 Generic Router Architecture-----------------------31 3.2 Motivation----------------------------------------36 3.3 Format of the Packet------------------------------37 3.4 Concept of the Even-Odd Turn Model----------------40 3.5 Deadlock-Free of the Even-Odd Turn Model----------42 3.6 Deadlock-Free of the dynamic routing algorithm----44 3.7 Architecture of the Switch------------------------58 CHAPTER 4---------------------------------------------65 Experiment Results------------------------------------65 4.1 Estimation under Random Traffic-------------------65 4.2 Estimation of the Multimedia Traffic--------------71 CHAPTER 5---------------------------------------------75 Conclusion--------------------------------------------75 REFERENCE---------------------------------------------77 | |
| dc.language.iso | en | |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 晶片網路 | zh_TW |
| dc.subject | 網狀物 | zh_TW |
| dc.subject | 路徑演算法 | zh_TW |
| dc.subject | Mesh | en |
| dc.subject | Low power | en |
| dc.subject | routing algorithm | en |
| dc.subject | Network-on-Chip | en |
| dc.title | 有效率網路晶片路徑策略的動態交換器架構 | zh_TW |
| dc.title | An Efficient Routing Strategy for Networks-on-Chip with the Dynamic Architecture of the Switch | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 95-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 顧孟愷(Mong-kai Ku),張延任(Yen-Jen Chang),張孟洲(Meng-Zhou Zhang) | |
| dc.subject.keyword | 晶片網路,網狀物,路徑演算法,低功率, | zh_TW |
| dc.subject.keyword | Network-on-Chip,Mesh,routing algorithm,Low power, | en |
| dc.relation.page | 78 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2007-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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